Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS92LV1212

DS92LV1212

更新时间： 2024-01-14 03:43:20

品牌	Logo	应用领域
美国国家半导体 - NSC		时钟
页数	文件大小	规格书
13页	320K
描述
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery

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技术参数
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DS92LV1212 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	SSOP, SSOP28,.3
针数：	28	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE RECEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	10.2 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：		接收器位数：	1
座面最大高度：	2 mm	子类别：	Line Driver or Receivers
最大压摆率：	60 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	5.29 mm
Base Number Matches：	1

DS92LV1212 数据手册

April 1999

DS92LV1212

16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer

with Embedded Clock Recovery

General Description

Features

n Clock recovery without SYNC patterns-random lock

n Guaranteed transition every data transfer cycle

The DS92LV1212 is an upgrade of the DS92LV1210. It

maintains all of the features of the DS92LV1210 with the ad-

ditional capability of locking to the incoming data stream

without the need of SYNC patterns. This makes the

DS92LV1212 useful in applications where the Deserializer

must be operated “open-loop” — without a feedback path

from the Deserializer to the Serializer. The DS92LV1212 is

designed to be used with the DS92LV1021 Bus LVDS Serial-

izer. The DS92LV1212 receives a Bus LVDS serial data

stream and transforms it into a 10-bit wide parallel data bus

and separate clock. The reduced cable, PCB trace count

and connector size saves cost and makes PCB layout

easier. Clock-to-data and data-to-data skews are eliminated

since one input receives both clock and data bits serially.

The powerdown pin is used to save power by reducing the

supply current when the device is not in use. The Deserial-

izer will establish lock to a synchronization pattern within

specified lock times but it can also lock to a data stream with-

out SYNC patterns.

n Chipset (Tx + Rx) power consumption 300mW (typ)

40MHz

n Single differential pair eliminates multi-channel skew

n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)

n 10-bit parallel interface for 1 byte data plus 2 control bits

or UTOPIA I Interface

n Synchronization mode and LOCK indicator

n Flow-through pinout for easy PCB layout

n High impedance on receiver inputs when power is off

n Programmable edge trigger on clock

n Footprint compatible with DS92LV1210

n Small 28-lead SSOP package-MSA

Block Diagram

DS100982-1

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100982

www.national.com

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与DS92LV1212相关器件

型号	品牌	描述	获取价格	数据表
DS92LV1212_11	TI	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212A	NSC	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212A	TI	The DS92LV 1212A is an upgrade of the DS92LV1212.	获取价格
DS92LV1212AMSA	TI	DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recover	获取价格
DS92LV1212AMSA	NSC	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212AMSA/NOPB	NSC	IC LINE RECEIVER, PDSO28, EIAJ, SSOP-28, Line Driver or Receiver	获取价格

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