Datasheet > DS92LV1210TMSA

DS92LV1210TMSA

更新时间： 2024-02-28 08:44:49

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
18页	380K
描述
16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

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技术参数
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DS92LV1210TMSA 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP, SSOP28,.3	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.73
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE RECEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	10.2 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：		接收器位数：	1
座面最大高度：	2 mm	子类别：	Line Driver or Receivers
最大压摆率：	55 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	5.29 mm
Base Number Matches：	1

DS92LV1210TMSA 数据手册

December 2002

DS92LV1021 and DS92LV1210

16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

due to charged cable conditions. The DS92LV1021 output

General Description

pins may be TRI-STATE

to achieve a high impedance

The DS92LV1021 transforms a 10-bit wide parallel CMOS/

TTL data bus into a single high speed Bus LVDS serial data

stream with embedded clock. The DS92LV1210 receives the

Bus LVDS serial data stream and transforms it back into a

10-bit wide parallel data bus and separates clock. The

DS92LV1021 may transmit data over heavily loaded back-

planes or 10 meters of cable. The reduced cable, PCB trace

count and connector size saves cost and makes PCB design

layout easier. Clock-to-data and data-to-data skew are elimi-

nated since one output will transmit both clock and all data

bits serially. The powerdown pin is used to save power, by

reducing supply current when either device is not in use. The

Serializer has a synchronization mode that should be acti-

vated upon power-up of the device. The Deserializer will

establish lock to this signal within 1024 cycles, and will flag

Lock status. The embedded clock guarantees a transition on

the bus every 12-bit cycle; eliminating transmission errors

state. The PLL can lock to frequencies between 16 MHz and

40 MHz.

Features

n Guaranteed transition every data transfer cycle

n Single differential pair eliminates multi-channel skew

n Flow-through pinout for easy PCB layout

n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)

n 10-bit parallel interface for 1 byte data plus 2 control bits

n Synchronization mode and LOCK indicator

n Programmable edge trigger on clock

n High impedance on receiver inputs when power is off

n Bus LVDS serial output rated for 27Ω load

n Small 28-lead SSOP package-MSA

Block Diagrams

10011001

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100110

www.national.com

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与DS92LV1210TMSA相关器件

型号	品牌	描述	获取价格	数据表
DS92LV1210TMSA/NOPB	TI	LINE RECEIVER, PDSO28, SSOP-28	获取价格
DS92LV1212	NSC	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212	TI	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212_11	TI	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212A	NSC	16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery	获取价格
DS92LV1212A	TI	The DS92LV 1212A is an upgrade of the DS92LV1212.	获取价格

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