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DS92LV1023TMSA/NOPB PDF预览

DS92LV1023TMSA/NOPB

更新时间: 2024-11-18 13:07:27
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
20页 497K
描述
IC LINE DRIVER, PDSO28, SSOP-28, Line Driver or Receiver

DS92LV1023TMSA/NOPB 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:SSOP, SSOP28,.3Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
差分输出:YES驱动器位数:1
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
湿度敏感等级:3功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:2 mm子类别:Line Driver or Receivers
最大压摆率:90 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.29 mmBase Number Matches:1

DS92LV1023TMSA/NOPB 数据手册

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June 2002  
DS92LV1023 and DS92LV1224  
40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer  
conditions. Furthermore, you may put the DS92LV1023 out-  
General Description  
®
put pins into TRI-STATE  
to achieve a high impedance  
The DS92LV1023 transforms  
a 10-bit wide parallel  
state. The PLL can lock to frequencies between 40 MHz and  
66 MHz.  
LVCMOS/LVTTL data bus into a single high speed Bus  
LVDS serial data stream with embedded clock. The  
DS92LV1224 receives the Bus LVDS serial data stream and  
transforms it back into a 10-bit wide parallel data bus and  
recovers parallel clock. The DS92LV1023 transmits data  
over backplanes or cable. The single differential pair data  
path makes PCB design easier. In addition, the reduced  
cable, PCB trace count, and connector size tremendously  
reduce cost. Since one output transmits clock and data bits  
serially, it eliminates clock-to-data and data-to-data skew.  
The powerdown pin saves power by reducing supply current  
when not using either device. Upon power up of the Serial-  
izer, you can choose to activate synchronization mode or  
Features  
n Clock recovery from PLL lock to random data patterns.  
n Guaranteed transition every data transfer cycle  
<
n Chipset (Tx + Rx) power consumption 500 mW (typ)  
@
66 MHz  
n Single differential pair eliminates multi-channel skew  
n Flow-through pinout for easy PCB layout  
n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock)  
n 10-bit parallel interface for 1 byte data plus 2 control bits  
n Synchronization mode and LOCK indicator  
n Programmable edge trigger on clock  
n High impedance on receiver inputs when power is off  
n Bus LVDS serial output rated for 27load  
n Small 28-lead SSOP package  
allow  
the  
Deserializer  
to  
use  
the  
synchronization-to-random-data feature. By using the syn-  
chronization mode, the Deserializer will establish lock to a  
signal within specified lock times. In addition, the embedded  
clock guarantees a transition on the bus every 12-bit cycle.  
This eliminates transmission errors due to charged cable  
Block Diagrams  
10093301  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2002 National Semiconductor Corporation  
DS100933  
www.national.com  

DS92LV1023TMSA/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS92LV1023TMSA NSC

完全替代

40-66 MHz 10 Bit Bus LVDS Serializer and Deserializer

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DS92LV1210TMSA/NOPB TI

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16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
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16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
DS92LV1212_11 TI

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16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
DS92LV1212A NSC

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16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
DS92LV1212A TI

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The DS92LV 1212A is an upgrade of the DS92LV1212.
DS92LV1212AMSA TI

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DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recover