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DS92LV040 PDF预览

DS92LV040

更新时间: 2024-02-05 19:42:05
品牌 Logo 应用领域
美国国家半导体 - NSC 总线收发器
页数 文件大小 规格书
12页 219K
描述
4 Channel Bus LVDS Transceiver

DS92LV040 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:VQCCN, LCC44,.28SQ,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.36差分输出:YES
驱动器位数:4高电平输入电流最大值:0.00002 A
输入特性:DIFFERENTIAL接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PQCC-N44
JESD-609代码:e3长度:7 mm
湿度敏感等级:2功能数量:4
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:0.2 V
最大输出低电流:0.004 A封装主体材料:PLASTIC/EPOXY
封装代码:VQCCN封装等效代码:LCC44,.28SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:3.2 ns
接收器位数:4座面最大高度:0.8 mm
子类别:Line Driver or Receivers最大压摆率:100 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40最大传输延迟:2.3 ns
宽度:7 mmBase Number Matches:1

DS92LV040 数据手册

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August 2002  
DS92LV040A  
4 Channel Bus LVDS Transceiver  
General Description  
Features  
n Bus LVDS Signaling  
The DS92LV040A is one in a series of Bus LVDS transceiv-  
ers designed specifically for high speed, low power back-  
plane or cable interfaces. The device operates from a single  
3.3V power supply and includes four differential line drivers  
and four receivers. To minimize bus loading, the driver out-  
puts and receiver inputs are internally connected. The device  
also features a flow through pin out which allows easy PCB  
routing for short stubs between its pins and the connector.  
n Propagation delay: Driver 2.3ns max, Receiver 3.2ns  
max  
n Low power CMOS design  
n 100% Transition time 1ns driver typical, 1.3ns receiver  
typical  
n High Signaling Rate Capability (above 155 Mbps)  
n 0.1V to 2.3V Common Mode Range for VID = 200mV  
n 70 mV Receiver Sensitivity  
n Supports open and terminated failsafe on port pins  
n 3.3V operation  
n Glitch free power up/down (Driver & Receiver disabled)  
n Light Bus Loading (5 pF typical) per Bus LVDS load  
n Designed for Double Termination Applications  
n Balanced Output Impedance  
The driver translates 3V LVTTL levels (single-ended) to dif-  
ferential Bus LVDS (BLVDS) output levels. This allows for  
high speed operation while consuming minimal power and  
reducing EMI. In addition, the differential signaling provides  
common mode noise rejection greater than 1V.  
The receiver threshold is less than +0/−70 mV. The receiver  
translates the differential Bus LVDS to standard (LVTTL/  
LVCMOS) levels. (See Applications Information Section for  
more details.)  
n Product offered in 44 pin LLP (Leadless Leadframe  
Package) package  
n High impedance Bus pins on power off (VCC = 0V)  
Simplified Functional Diagram  
10133601  
© 2002 National Semiconductor Corporation  
DS101336  
www.national.com  

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