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DS90UB913Q

更新时间: 2024-09-27 12:55:27
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
5页 182K
描述
10-100MHz 10/12-Bit FPD-Link III SER/DES

DS90UB913Q 数据手册

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DS90UB913Q/DS90UB914Q  
PRODUCT BRIEF  
10-100MHz 10/12-Bit FPD-Link III SER/DES  
General Description  
Features  
The DS90UB913Q/DS90UB914Q chipset offers a FPD-Link  
III interface with a high-speed forward channel and a bidirec-  
tional control channel for data transmission over a single  
differential pair. The DS90UB913Q/914Q chipsets incorpo-  
rate differential signaling on both the high-speed forward  
channel and bidirectional control channel data paths. The Se-  
rializer/ Deserializer pair is targeted for connections between  
imagers and video processors in an ECU (Electronic Control  
Unit). This chipset is ideally suited for driving video data re-  
quiring up to 12 bit pixel depth plus two synchronization  
signals along with bidirectional control channel bus.  
10 MHz to 100 MHz input pixel clock support  
Single differential pair interconnect  
Programmable data payload:  
10 bit payload up to 100Mhz  
12 bit payload up to 75MHz  
Continuous Low Latency Bidirectional control interface  
channel with I2C support@400kHz  
2:1 Multiplexer to choose between two input imagers  
Embedded clock with DC Balanced coding to support AC-  
coupled interconnects  
There is a multiplexer at the Deserializer to choose between  
two input imagers. The Deserializer can have only one active  
input imager. The primary video transport converts 10/12 bit  
data over a single high-speed serial stream, along with a sep-  
arate low latency bidirectional control channel transport that  
accepts control information from an I2C port and is indepen-  
dent of video blanking period.  
Capable of driving up to 25 meters shielded twisted-pair  
4 dedicated General Purpose Input (GPI)/ Output (GPO)  
LOCK output reporting pin and AT-SPEED BIST diagnosis  
feature to validate link integrity  
Integrated termination resistors  
1.8V, 2.8V or 3.3V compatible parallel inputs on Serializer  
Single power supply at 1.8V  
Using TI’s embedded clock technology allows transparent full-  
duplex communication over a single differential pair, carrying  
asymmetrical bidirectional control channel information in both  
directions. This single serial stream simplifies transferring a  
wide data bus over PCB traces and cable by eliminating the  
skew problems between parallel data and clock paths. This  
significantly saves system cost by narrowing data paths that  
in turn reduce PCB layers, cable width, and connector size  
and pins. In addition, the Deserializer inputs provide adaptive  
equalization to compensate for loss from the media over  
longer distances. Internal DC balanced encoding/decoding is  
used to support AC-Coupled interconnects. The Serializer is  
offered in a 32-pin LLP package and the Deserializer is of-  
fered in a 48-pin LLP package.  
ISO 10605 and IEC 61000-4-2 ESD Compliant  
Temperature range −40°C to +105°C  
Small serializer footprint (5mm x 5mm)  
No reference clock required on Deserializer  
Adaptive Receive Equalization  
EMI/EMC Mitigation  
DES Programmable Spread Spectrum (SSCG)  
outputs.  
DES Receiver staggered outputs  
Applications  
Notice: This document is not a datasheet. For more in-  
formation regarding this product or to order samples  
please contact your local Texas Instruments sales office  
or visit http://focus.ti.com/general/ docs/dsnsuprt.tsp.  
Automotive Vision Systems  
Front camera for collision mitigation  
Rear view camera for backup protection  
Parking Assistance  
Typical Application Diagram  
30144627  
PRODUCTION DATA information is current as of  
publication date. Products conform to specifications per  
the terms of the Texas Instruments standard warranty.  
Production processing does not necessarily include  
testing of all parameters.  
301446 SNLS420  
Copyright © 1999-2012, Texas Instruments Incorporated  

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