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DS90LV049TMT PDF预览

DS90LV049TMT

更新时间: 2024-11-15 22:26:19
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器接口集成电路光电二极管
页数 文件大小 规格书
10页 228K
描述
3V LVDS Dual Line Driver with Dual Line Receiver

DS90LV049TMT 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.100 INCH, TSSOP-16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:3.1差分输出:YES
驱动器位数:2高电平输入电流最大值:0.00001 A
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-644-A; TIA-644-AJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
湿度敏感等级:1功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:0.25 V
最大输出低电流:0.002 A封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:3.5 ns
接收器位数:2座面最大高度:1.1 mm
子类别:Line Driver or Receivers最大压摆率:35 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40最大传输延迟:2 ns
宽度:4.4 mmBase Number Matches:1

DS90LV049TMT 数据手册

 浏览型号DS90LV049TMT的Datasheet PDF文件第2页浏览型号DS90LV049TMT的Datasheet PDF文件第3页浏览型号DS90LV049TMT的Datasheet PDF文件第4页浏览型号DS90LV049TMT的Datasheet PDF文件第5页浏览型号DS90LV049TMT的Datasheet PDF文件第6页浏览型号DS90LV049TMT的Datasheet PDF文件第7页 
March 2003  
DS90LV049  
3V LVDS Dual Line Driver with Dual Line Receiver  
General Description  
Features  
n Up to 400 Mbps switching rates  
n Flow-through pinout simplifies PCB layout  
n 50 ps typical driver channel-to-channel skew  
The DS90LV049 is a dual CMOS flow-through differential  
line driver-receiver pair designed for applications requiring  
ultra low power dissipation, exceptional noise immunity, and  
high data throughput. The device is designed to support data  
rates in excess of 400 Mbps utilizing Low Voltage Differential  
Signaling (LVDS) technology.  
n 50 ps typical receiver channel-to-channel skew  
n 3.3 V single power supply design  
n TRI-STATE output control  
The DS90LV049 drivers accept LVTTL/LVCMOS signals and  
translate them to LVDS signals. On the other hand, the  
receivers accept LVDS signals and translate them to 3 V  
CMOS signals. The LVDS input buffers have internal failsafe  
biasing that places the outputs to a known H (high) state for  
floating receiver inputs. In addition, the DS90LV049 supports  
a TRI-STATE function for a low idle power state when the  
device is not in use.  
n Internal fail-safe biasing of receiver inputs  
n Low power dissipation (70 mW at 3.3 V static)  
n High impedance on LVDS outputs on power down  
n Conforms to TIA/EIA-644-A LVDS Standard  
n Industrial operating temperature range (−40˚C to +85˚C)  
n Available in low profile 16 pin TSSOP package  
The EN and EN inputs are ANDed together and control the  
TRI-STATE outputs. The enables are common to all four  
gates.  
Connection Diagram  
Functional Diagram  
Dual-In-Line  
20042001  
Order Number DS90LV049TMT  
Order Number DS90LV049TMTX (Tape and Reel)  
See NS Package Number MTC16  
20042002  
Truth Table  
EN  
L or Open  
H
EN  
L or Open  
L or Open  
H
LVDS Out  
OFF  
LVCMOS Out  
OFF  
ON  
ON  
L or Open  
H
OFF  
OFF  
H
OFF  
OFF  
© 2003 National Semiconductor Corporation  
DS200420  
www.national.com  

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