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DS90LV001TMX/NOPB PDF预览

DS90LV001TMX/NOPB

更新时间： 2024-10-27 18:11:27
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
16页 456K
描述
IC LINE RECEIVER, PDSO8, SOIC-8, Line Driver or Receiver

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DS90LV001TMX/NOPB 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：SOP, SOP8,.25Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.27差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00002 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.25 V
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：2 ns接收器位数：1
座面最大高度：1.75 mm子类别：Line Driver or Receivers
最大压摆率：70 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

DS90LV001TMX/NOPB 数据手册

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February 19, 2008  
DS90LV001  
800 Mbps LVDS Buffer  
General Description  
An output enable pin is provided, which allows the user to  
place the LVDS output in TRI-STATE.  
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input  
signal and provides an LVDS output signal. In many large  
systems, signals are distributed across backplanes, and one  
of the limiting factors for system speed is the "stub length" or  
the distance between the transmission line and the untermi-  
nated receivers on individual cards. Although it is generally  
recognized that this distance should be as short as possible  
to maximize system performance, real-world packaging con-  
cerns often make it difficult to make the stubs as short as the  
designer would like.  
The DS90LV001 is offered in two package options, an 8 pin  
LLP and SOIC.  
Features  
Single +3.3 V Supply  
■
■
■
■
■
■
■
LVDS receiver inputs accept LVPECL signals  
TRI-STATE outputs  
Receiver input threshold < ±100 mV  
Fast propagation delay of 1.4 ns (typ)  
The DS90LV001, available in the LLP (Leadless Leadframe  
Package) package, will allow the receiver to be placed very  
close to the main transmission line, thus improving system  
performance.  
Low jitter 800 Mbps fully differential data path  
100 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern  
at 800 Mbps  
A wide input dynamic range will allow the DS90LV001 to re-  
ceive differential signals from LVPECL as well as LVDS  
sources. This will allow the device to also fill the role of an  
LVPECL-LVDS translator.  
Compatible with ANSI/TIA/EIA-644-A LVDS standard  
■
■
■
8 pin SOIC and space saving (70%) LLP package  
Industrial Temperature Range  
Connection Diagram  
Top View  
10133805  
Order Number DS90LV001TM, DS90LV001TLD  
See NS Package Number M08A, LDA08A  
Block Diagram  
10133802  
© 2008 National Semiconductor Corporation  
101338  
www.national.com  
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DS90LV004_07 NSC

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DS90LV004TVS NSC

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DS90LV004TVS TI

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 		具有预加重功能的 4 通道 LVDS 缓冲器/中继器 | PFB | 48 | -40 t
DS90LV004TVS/NOPB TI

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 		具有预加重功能的 4 通道 LVDS 缓冲器/中继器 | PFB | 48 | -40 t
DS90LV011A NSC

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 		3V LVDS Single High Speed Differential Driver
DS90LV011A TI

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 		DS90LV011A 3V LVDS Single High Speed Differential Driver
DS90LV011A_16 TI

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 		3V LVDS Single High Speed Differential Driver
DS90LV011AH NSC

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 		HIGH TEMPERATURE 3V LVDS DIFFERENTIAL DRIVER

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