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DS90LV001TMX PDF预览

DS90LV001TMX

更新时间: 2024-10-27 21:11:19
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
13页 395K
描述
IC LINE RECEIVER, PDSO8, SOIC-8, Line Driver or Receiver

DS90LV001TMX 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOIC-8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.27差分输出:YES
驱动器位数:1高电平输入电流最大值:0.00002 A
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644-A; TIA-644-AJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:0.25 V
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):235
电源:3.3 V认证状态:Not Qualified
最大接收延迟:2 ns接收器位数:1
座面最大高度:1.75 mm子类别:Line Driver or Receivers
最大压摆率:70 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

DS90LV001TMX 数据手册

 浏览型号DS90LV001TMX的Datasheet PDF文件第2页浏览型号DS90LV001TMX的Datasheet PDF文件第3页浏览型号DS90LV001TMX的Datasheet PDF文件第4页浏览型号DS90LV001TMX的Datasheet PDF文件第5页浏览型号DS90LV001TMX的Datasheet PDF文件第6页浏览型号DS90LV001TMX的Datasheet PDF文件第7页 
April 2001  
DS90LV001  
3.3V LVDS-LVDS Buffer  
General Description  
An output enable pin is provided, which allows the user to  
place the LVDS output in TRI-STATE.  
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input  
signal and provides an LVDS output signal. In many large  
systems, signals are distributed across backplanes, and one  
of the limiting factors for system speed is the ’stub length’ or  
the distance between the transmission line and the untermi-  
nated receivers on individual cards. Although it is generally  
recognized that this distance should be as short as possible  
to maximize system performance, real-world packaging con-  
cerns often make it difficult to make the stubs as short as the  
designer would like.  
The DS90LV001 is offered in two package options, an 8 pin  
LLP and SOIC.  
Features  
n Single +3.3 V Supply  
n LVDS receiver inputs accept LVPECL signals  
n TRI-STATE outputs  
<
±
n Receiver input threshold  
100 mV  
n Fast propagation delay of 1.4 ns (typ)  
n Low jitter 800 Mbps fully differential data path  
n 100 ps (typ) of pk-pk jitter with PRBS = 223−1 data  
pattern at 800 Mbps  
n Compatible with ANSI/TIA/EIA-644-A LVDS standard  
n 8 pin SOIC and space saving (70%) LLP package  
n Industrial Temperature Range  
The DS90LV001, available in the LLP (Leadless Leadframe  
Package) package, will allow the receiver to be placed very  
close to the main transmission line, thus improving system  
performance.  
A wide input dynamic range will allow the DS90LV001 to  
receive differential signals from LVPECL as well as LVDS  
sources. This will allow the device to also fill the role of an  
LVPECL-LVDS translator.  
Connection Diagram  
Top View  
DS101338-5  
Order Number DS90LV001TM, DS90LV001TLD  
See NS Package Number M08A, LDA08A  
Block Diagram  
DS101338-2  
© 2001 National Semiconductor Corporation  
DS101338  
www.national.com  

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