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DS90LV001TLD/NOPB PDF预览

DS90LV001TLD/NOPB

更新时间： 2024-10-27 13:07:27
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
21页 1302K
描述
800-Mbps LVDS buffer 8-WSON -40 to 85

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DS90LV001TLD/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：HVSON, SOLCC8,.11,20针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.05差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00002 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：S-PDSO-N8
JESD-609代码：e3长度：3 mm
湿度敏感等级：3功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.25 V
最大输出低电流：0.00001 A封装主体材料：PLASTIC/EPOXY
封装代码：HVSON封装等效代码：SOLCC8,.11,20
封装形状：SQUARE封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：2 ns
接收器位数：1座面最大高度：0.8 mm
子类别：Line Driver or Receivers最大压摆率：70 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

DS90LV001TLD/NOPB 数据手册

 浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第2页浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第3页浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第4页浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第5页浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第6页浏览型号DS90LV001TLD/NOPB的Datasheet PDF文件第7页 
DS90LV001  
www.ti.com  
SNLS067E –JANUARY 2001–REVISED APRIL 2013  
DS90LV001 800 Mbps LVDS Buffer  
Check for Samples: DS90LV001  
1
FEATURES  
DESCRIPTION  
The DS90LV001 LVDS-LVDS Buffer takes an LVDS  
input signal and provides an LVDS output signal. In  
many large systems, signals are distributed across  
backplanes, and one of the limiting factors for system  
speed is the "stub length" or the distance between  
the transmission line and the unterminated receivers  
on individual cards. Although it is generally  
recognized that this distance should be as short as  
possible to maximize system performance, real-world  
packaging concerns often make it difficult to make the  
stubs as short as the designer would like.  
2
•
•
•
•
•
•
Single +3.3 V Supply  
LVDS Receiver Inputs Accept LVPECL Signals  
TRI-STATE Outputs  
Receiver Input Threshold < ±100 mV  
Fast Propagation Delay of 1.4 ns (Typ)  
Low Jitter 800 Mbps Fully Differential Data  
Path  
100 ps (Typ) of pk-pk Jitter with PRBS = 223−1  
•
•
•
•
Data Pattern at 800 Mbps  
The DS90LV001, available in the WSON package,  
will allow the receiver to be placed very close to the  
main transmission line, thus improving system  
performance.  
Compatible with ANSI/TIA/EIA-644-A LVDS  
Standard  
8 pin SOIC and Space Saving (70%) WSON  
Package  
A
wide input dynamic range will allow the  
Industrial Temperature Range  
DS90LV001 to receive differential signals from  
LVPECL as well as LVDS sources. This will allow the  
device to also fill the role of an LVPECL-LVDS  
translator.  
An output enable pin is provided, which allows the  
user to place the LVDS output in TRI-STATE.  
The DS90LV001 is offered in two package options,  
an 8 pin WSON and SOIC.  
Connection Diagram  
Figure 1. Top View  
See Package Number D (R-PDSO-G8), NGK0008A  
Block Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2013, Texas Instruments Incorporated  
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DS90LV001TLD/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90LV001TLDX/NOPB TI

类似代替

 800 Mbps LVDS Buffer
DS90LV001TLD TI

类似代替

 DS90LV001 800 Mbps LVDS Buffer

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 		IC LINE RECEIVER, PDSO8, SOIC-8, Line Driver or Receiver
DS90LV001TMX/NOPB NSC

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 		IC LINE RECEIVER, PDSO8, SOIC-8, Line Driver or Receiver

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