Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90LV001MWC

DS90LV001MWC

更新时间： 2024-10-27 12:59:43

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
21页	1302K
描述
LINE RECEIVER, UUC, WAFER

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技术参数
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DS90LV001MWC 技术参数

生命周期：	Obsolete	零件包装代码：	WAFER
包装说明：	DIE,	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.54	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644-A; TIA-644-A
JESD-30 代码：	X-XUUC-N	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	DIE
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
认证状态：	Not Qualified	最大接收延迟：	2 ns
接收器位数：	1	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

DS90LV001MWC 数据手册

DS90LV001

www.ti.com

SNLS067E –JANUARY 2001–REVISED APRIL 2013

DS90LV001 800 Mbps LVDS Buffer

Check for Samples: DS90LV001

FEATURES

DESCRIPTION

The DS90LV001 LVDS-LVDS Buffer takes an LVDS

input signal and provides an LVDS output signal. In

many large systems, signals are distributed across

backplanes, and one of the limiting factors for system

speed is the "stub length" or the distance between

the transmission line and the unterminated receivers

on individual cards. Although it is generally

recognized that this distance should be as short as

possible to maximize system performance, real-world

packaging concerns often make it difficult to make the

stubs as short as the designer would like.

•

Single +3.3 V Supply

LVDS Receiver Inputs Accept LVPECL Signals

TRI-STATE Outputs

Receiver Input Threshold < ±100 mV

Fast Propagation Delay of 1.4 ns (Typ)

Low Jitter 800 Mbps Fully Differential Data

Path

100 ps (Typ) of pk-pk Jitter with PRBS = 2²³−1

•

Data Pattern at 800 Mbps

The DS90LV001, available in the WSON package,

will allow the receiver to be placed very close to the

main transmission line, thus improving system

performance.

Compatible with ANSI/TIA/EIA-644-A LVDS

Standard

8 pin SOIC and Space Saving (70%) WSON

Package

wide input dynamic range will allow the

Industrial Temperature Range

DS90LV001 to receive differential signals from

LVPECL as well as LVDS sources. This will allow the

device to also fill the role of an LVPECL-LVDS

translator.

An output enable pin is provided, which allows the

user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options,

an 8 pin WSON and SOIC.

Connection Diagram

Figure 1. Top View

See Package Number D (R-PDSO-G8), NGK0008A

Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...21

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与DS90LV001MWC相关器件

型号	品牌	获取价格	描述	数据表
DS90LV001TLD	NSC	获取价格	3.3V LVDS-LVDS Buffer
DS90LV001TLD	TI	获取价格	DS90LV001 800 Mbps LVDS Buffer
DS90LV001TLD/NOPB	NSC	获取价格	IC LINE RECEIVER, PDSO8, LLP-8, Line Driver or Receiver
DS90LV001TLD/NOPB	TI	获取价格	800-Mbps LVDS buffer 8-WSON -40 to 85
DS90LV001TLDX	NSC	获取价格	暂无描述
DS90LV001TLDX/NOPB	NSC	获取价格	IC LINE RECEIVER, PDSO8, LLP-8, Line Driver or Receiver
DS90LV001TLDX/NOPB	TI	获取价格	800 Mbps LVDS Buffer
DS90LV001TM	TI	获取价格	DS90LV001 800 Mbps LVDS Buffer
DS90LV001TM	NSC	获取价格	3.3V LVDS-LVDS Buffer
DS90LV001TM/NOPB	TI	获取价格	800 Mbps LVDS Buffer

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