Datasheet > DS90LV001MDC

DS90LV001MDC

更新时间： 2024-10-27 21:11:19

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动接口集成电路驱动器
页数	文件大小	规格书
13页	395K
描述
IC LINE RECEIVER, UUC, DIE, Line Driver or Receiver

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS90LV001MDC 技术参数

生命周期：	Transferred	包装说明：	DIE, DIE OR CHIP
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.54
差分输出：	YES	驱动器位数：	1
高电平输入电流最大值：	0.00002 A	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644-A; TIA-644-A
JESD-30 代码：	X-XUUC-N	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
最小输出摆幅：	0.25 V	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：	2 ns	接收器位数：	1
子类别：	Line Driver or Receivers	最大压摆率：	70 mA
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子位置：	UPPER
Base Number Matches：	1

DS90LV001MDC 数据手册

April 2001

DS90LV001

3.3V LVDS-LVDS Buffer

General Description

An output enable pin is provided, which allows the user to

place the LVDS output in TRI-STATE.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input

signal and provides an LVDS output signal. In many large

systems, signals are distributed across backplanes, and one

of the limiting factors for system speed is the ’stub length’ or

the distance between the transmission line and the untermi-

nated receivers on individual cards. Although it is generally

recognized that this distance should be as short as possible

to maximize system performance, real-world packaging con-

cerns often make it difficult to make the stubs as short as the

designer would like.

The DS90LV001 is offered in two package options, an 8 pin

LLP and SOIC.

Features

n Single +3.3 V Supply

n LVDS receiver inputs accept LVPECL signals

n TRI-STATE outputs

n Receiver input threshold

100 mV

n Fast propagation delay of 1.4 ns (typ)

n Low jitter 800 Mbps fully differential data path

n 100 ps (typ) of pk-pk jitter with PRBS = 2²³−1 data

pattern at 800 Mbps

n Compatible with ANSI/TIA/EIA-644-A LVDS standard

n 8 pin SOIC and space saving (70%) LLP package

n Industrial Temperature Range

The DS90LV001, available in the LLP (Leadless Leadframe

Package) package, will allow the receiver to be placed very

close to the main transmission line, thus improving system

performance.

A wide input dynamic range will allow the DS90LV001 to

receive differential signals from LVPECL as well as LVDS

sources. This will allow the device to also fill the role of an

LVPECL-LVDS translator.

Connection Diagram

Top View

DS101338-5

Order Number DS90LV001TM, DS90LV001TLD

See NS Package Number M08A, LDA08A

Block Diagram

DS101338-2

DS101338

www.national.com

12 3 4 5 6 7...13

中文翻译

下载PDF

与DS90LV001MDC相关器件

型号	品牌	获取价格	描述	数据表
DS90LV001MWC	TI	获取价格	LINE RECEIVER, UUC, WAFER
DS90LV001MWC	NSC	获取价格	IC LINE RECEIVER, UUC, WAFER, Line Driver or Receiver
DS90LV001TLD	NSC	获取价格	3.3V LVDS-LVDS Buffer
DS90LV001TLD	TI	获取价格	DS90LV001 800 Mbps LVDS Buffer
DS90LV001TLD/NOPB	NSC	获取价格	IC LINE RECEIVER, PDSO8, LLP-8, Line Driver or Receiver
DS90LV001TLD/NOPB	TI	获取价格	800-Mbps LVDS buffer 8-WSON -40 to 85
DS90LV001TLDX	NSC	获取价格	暂无描述
DS90LV001TLDX/NOPB	NSC	获取价格	IC LINE RECEIVER, PDSO8, LLP-8, Line Driver or Receiver
DS90LV001TLDX/NOPB	TI	获取价格	800 Mbps LVDS Buffer
DS90LV001TM	TI	获取价格	DS90LV001 800 Mbps LVDS Buffer

与DS90LV001MDC相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

11
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

10
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

37
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

45

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90LV001MDC

DS90LV001MDC 技术参数

DS90LV001MDC 数据手册

与DS90LV001MDC相关器件

与DS90LV001MDC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90LV001MDC

DS90LV001MDC 技术参数

DS90LV001MDC 数据手册

与DS90LV001MDC相关器件

与DS90LV001MDC相关文章

您还可以找

您在本页遇到什么问题？