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DS90LV001_08

更新时间: 2024-10-27 04:39:15
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美国国家半导体 - NSC /
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16页 508K
描述
800 Mbps LVDS Buffer

DS90LV001_08 数据手册

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February 19, 2008  
DS90LV001  
800 Mbps LVDS Buffer  
General Description  
An output enable pin is provided, which allows the user to  
place the LVDS output in TRI-STATE.  
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input  
signal and provides an LVDS output signal. In many large  
systems, signals are distributed across backplanes, and one  
of the limiting factors for system speed is the "stub length" or  
the distance between the transmission line and the untermi-  
nated receivers on individual cards. Although it is generally  
recognized that this distance should be as short as possible  
to maximize system performance, real-world packaging con-  
cerns often make it difficult to make the stubs as short as the  
designer would like.  
The DS90LV001 is offered in two package options, an 8 pin  
LLP and SOIC.  
Features  
Single +3.3 V Supply  
LVDS receiver inputs accept LVPECL signals  
TRI-STATE outputs  
Receiver input threshold < ±100 mV  
Fast propagation delay of 1.4 ns (typ)  
The DS90LV001, available in the LLP (Leadless Leadframe  
Package) package, will allow the receiver to be placed very  
close to the main transmission line, thus improving system  
performance.  
Low jitter 800 Mbps fully differential data path  
100 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern  
at 800 Mbps  
A wide input dynamic range will allow the DS90LV001 to re-  
ceive differential signals from LVPECL as well as LVDS  
sources. This will allow the device to also fill the role of an  
LVPECL-LVDS translator.  
Compatible with ANSI/TIA/EIA-644-A LVDS standard  
8 pin SOIC and space saving (70%) LLP package  
Industrial Temperature Range  
Connection Diagram  
Top View  
10133805  
Order Number DS90LV001TM, DS90LV001TLD  
See NS Package Number M08A, LDA08A  
Block Diagram  
10133802  
© 2008 National Semiconductor Corporation  
101338  
www.national.com  

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