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DS90CR287SLC/NOPB PDF预览

DS90CR287SLC/NOPB

更新时间: 2024-09-15 12:33:35
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
24页 1209K
描述
DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link - 85MHz

DS90CR287SLC/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:BGA
包装说明:LFBGA, BGA64,8X8,32针数:64
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:8.11差分输出:YES
驱动器位数:4输入特性:STANDARD
接口集成电路类型:LINE DRIVER接口标准:EIA-644; TIA-644
JESD-30 代码:S-PBGA-B64JESD-609代码:e1
长度:8 mm湿度敏感等级:4
功能数量:1端子数量:64
最高工作温度:70 °C最低工作温度:-10 °C
最小输出摆幅:2.7 V输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA64,8X8,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:1.5 mm子类别:Line Driver or Receivers
最大压摆率:60 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:1.5 ns
宽度:8 mmBase Number Matches:1

DS90CR287SLC/NOPB 数据手册

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DS90CR287, DS90CR288A  
www.ti.com  
SNLS056G OCTOBER 1999REVISED MARCH 2013  
DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS  
28-Bit Channel Link - 85MHz  
Check for Samples: DS90CR287, DS90CR288A  
1
FEATURES  
DESCRIPTION  
The DS90CR287 transmitter converts 28 bits of  
20 to 85 MHz Shift Clock Support  
LVCMOS/LVTTL data into four LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over a fifth LVDS link. Every cycle of the  
transmit clock 28 bits of input data are sampled and  
transmitted.  
50% Duty Cycle on Receiver Output Clock  
2.5 / 0 ns Set & Hold Times on TxINPUTs  
Low Power Consumption  
±1V Common-Mode Range (around +1.2V)  
Narrow Bus Reduces Cable Size and Cost  
Up to 2.38 Gbps Throughput  
The DS90CR288A receiver converts the four LVDS  
data streams back into 28 bits of LVCMOS/LVTTL  
data. At a transmit clock frequency of 85 MHz, 28 bits  
of TTL data are transmitted at a rate of 595 Mbps per  
LVDS data channel. Using a 85 MHz clock, the data  
throughput is 2.38 Gbit/s (297.5 Mbytes/sec).  
Up to 297.5 Mbytes/sec Bandwidth  
345 mV (typ) Swing LVDS Devices for Low EMI  
PLL Requires no External Components  
Rising Edge Data Strobe  
This chipset is an ideal means to solve EMI and  
cable size problems associated with wide, high-speed  
TTL interfaces.  
Compatible with TIA/EIA-644 LVDS Standard  
Low Profile 56-Lead TSSOP Package  
Block Diagram  
Figure 1. DS90CR287  
See Package Number DGG-56 (TSSOP)  
Figure 2. DS90CR288A  
See Package Number DGG-56 (TSSOP)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2013, Texas Instruments Incorporated  

DS90CR287SLC/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90CR287SLCX NSC

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IC LINE DRIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver

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