Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90CR284MWC

DS90CR284MWC

更新时间： 2024-11-05 13:07:27

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
13页	277K
描述
IC QUAD LINE RECEIVER, UUC, WAFER, Line Driver or Receiver

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技术参数
数据手册

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DS90CR284MWC 技术参数

生命周期：	Obsolete	包装说明：	DIE, DIE OR CHIP
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.7
输入特性：	DIFFERENTIAL	接口集成电路类型：	LINE RECEIVER
接口标准：	EIA-644; TIA-644	JESD-30 代码：	X-XUUC-N
功能数量：	4	最高工作温度：	70 °C
最低工作温度：	-10 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
电源：	5 V	认证状态：	Not Qualified
最大接收延迟：		接收器位数：	4
子类别：	Line Driver or Receivers	最大压摆率：	140 mA
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子位置：	UPPER
Base Number Matches：	1

DS90CR284MWC 数据手册

July 2001

DS90CR283/DS90CR284

28-Bit Channel Link-66 MHz

General Description

The DS90CR283 transmitter converts 28 bits of CMOS/TTL

data into four LVDS (Low Voltage Differential Signaling) data

streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fifth LVDS link. Every

cycle of the transmit clock 28 bits of input data are sampled

and transmitted. The DS90CR284 receiver converts the

LVDS data streams back into 28 bits of CMOS/TTL data. At

a transmit clock frequency of 66 MHz, 28 bits of TTL data are

transmitted at a rate of 462 Mbps per LVDS data channel.

Using a 66 MHz clock, the data throughput is 1.848 Gbit/s

(231 Mbytes/s).

width, which provides a system cost savings, reduces con-

nector physical size and cost, and reduces shielding require-

ments due to the cables’ smaller form factor.

The 28 CMOS/TTL inputs can support a variety of signal

combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +

parity) and 1 control.

Features

n 66 MHz clock support

n Up to 231 Mbytes/s bandwidth

n Low power CMOS design ( 610 mW)

n Power Down mode ( 0.5 mW total)

The multiplexing of the data lines provides a substantial

cable reduction. Long distance parallel single-ended buses

typically require a ground wire per active signal (and have

very limited noise rejection capability). Thus, for a 28-bit wide

data bus and one clock, up to 58 conductors are required.

With the Channel Link chipset as few as 11 conductors (4

data pairs, 1 clock pair and a minimum of one ground) are

needed. This provides a 80% reduction in required cable

n Up to 1.848 Gbit/s data throughput

n Narrow bus reduces cable size and cost

n 290 mV swing LVDS devices for low EMI

n PLL requires no external components

n Low profile 56-lead TSSOP package

n Rising edge data strobe

n Compatible with TIA/EIA-644 LVDS Standard

Block Diagrams

DS90CR283

DS90CR284

DS012889-27

DS012889-1

Order Number DS90CR283MTD

See NS Package Number MTD56

Order Number DS90CR284MTD

See NS Package Number MTD56

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS012889

www.national.com

12 3 4 5 6 7...13

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与DS90CR284MWC相关器件

型号	品牌	获取价格	描述	数据表
DS90CR285	NSC	获取价格	+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285	TI	获取价格	+3.3V 上升沿数据选通 LVDS 28 位 Channel Link 发送器 - 66
DS90CR285MTD	NSC	获取价格	+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285MTD	TI	获取价格	DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285MTD/NOPB	TI	获取价格	DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285MTDX	TI	获取价格	DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285MTDX/NOPB	TI	获取价格	DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR285SLC	NSC	获取价格	IC QUAD LINE DRIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver
DS90CR285SLCX	TI	获取价格	QUAD LINE DRIVER, PBGA64, 0.80 MM PITCH, FBGA-64
DS90CR286	NSC	获取价格	+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

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