5秒后页面跳转
DS90CR211 PDF预览

DS90CR211

更新时间: 2024-11-24 22:50:51
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
14页 258K
描述
21-Bit Channel Link

DS90CR211 数据手册

 浏览型号DS90CR211的Datasheet PDF文件第2页浏览型号DS90CR211的Datasheet PDF文件第3页浏览型号DS90CR211的Datasheet PDF文件第4页浏览型号DS90CR211的Datasheet PDF文件第5页浏览型号DS90CR211的Datasheet PDF文件第6页浏览型号DS90CR211的Datasheet PDF文件第7页 
July 1997  
DS90CR211/DS90CR212  
21-Bit Channel Link  
needed. This provides a 80% reduction in required cable  
width, providing a system cost savings, reduces connector  
physical size, and reduces shielding requirements due to the  
cables smaller form factor.  
General Description  
The DS90CR211 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR212 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 40 MHz, 21 bits of TTL data are  
transmitted at a rate of 280 Mbps per LVDS data channel.  
The 21 CMOS/TTL inputs can support a variety of signal  
combinations. For example, 5 4-bit nibbles plus 1 control, or  
2 9-bit (byte + parity) and 3 control.  
Features  
n Narrow bus reduces cable size and cost  
Using  
Mbit/s(105 Mbyte/s).  
a 40 MHz clock, the data throughput is 840  
±
n
1V Common mode range (ground shifting)  
n 290 mV swing LVDS data transmission  
n 840 Mbit/s data throughput  
n Low swing differential current mode drivers reduce EMI  
n Rising edge data strobe  
n Power down mode  
n Offered in low profile 48-lead TSSOP package  
The multiplexing of the data lines provides a substantial  
cable reduction. Long distance parallel single-ended buses  
typically require a ground wire per active signal (and have  
very limited noise rejection capability). Thus, for a 21-bit wide  
data bus and one clock, up to 44 conductors are required.  
With the Channel Link chipset as few as 9 conductors (3  
data pairs, 1 clock pair and a minimum of one ground) are  
Block Diagrams  
DS90CR211  
DS90CR212  
DS012637-27  
DS012637-1  
Order Number DS90CR211MTD  
See NS Package Number MTD48  
Order Number DS90CR212MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS012637  
www.national.com  

与DS90CR211相关器件

型号 品牌 获取价格 描述 数据表
DS90CR211MDC NSC

获取价格

IC TRIPLE LINE DRIVER, UUC, DIE, Line Driver or Receiver
DS90CR211MTD NSC

获取价格

21-Bit Channel Link
DS90CR211MTDX TI

获取价格

DS90CR211/DS90CR212 21-Bit Channel Link
DS90CR211MWC NSC

获取价格

暂无描述
DS90CR211MWC TI

获取价格

TRIPLE LINE DRIVER, UUC, WAFER
DS90CR212 TI

获取价格

DS90CR211/DS90CR212 21-Bit Channel Link
DS90CR212MTD NSC

获取价格

21-Bit Channel Link
DS90CR212MTDX TI

获取价格

QUAD LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48
DS90CR212MWC NSC

获取价格

TRIPLE LINE RECEIVER, UUC, WAFER
DS90CR213 NSC

获取价格

21-Bit Channel LinkΑ66 MHz