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DS90CF564MTD/NOPB PDF预览

DS90CF564MTD/NOPB

更新时间: 2024-09-15 21:06:51
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管接口集成电路
页数 文件大小 规格书
12页 287K
描述
IC QUAD LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48, Line Driver or Receiver

DS90CF564MTD/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.31输入特性:DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm湿度敏感等级:2
功能数量:4端子数量:48
最高工作温度:70 °C最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大接收延迟:接收器位数:4
座面最大高度:1.2 mm子类别:Line Driver or Receivers
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:6.1 mm
Base Number Matches:1

DS90CF564MTD/NOPB 数据手册

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July 1997  
DS90CF563/DS90CF564  
LVDS 18-Bit Color Flat Panel Display (FPD) Link—  
65 MHz  
General Description  
Features  
n 20 to 65 MHz shift clk support  
n Up to 171 Mbytes/s bandwidth  
n Cable size is reduced to save cost  
n 290 mV swing LVDS devices for low EMI  
The DS90CF563 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CF564 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 65 MHz, 18 bits of RGB data  
<
n Low power CMOS design ( 550 mW typ)  
n Power-down mode saves power ( 0.25 mW)  
<
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Falling edge data strobe  
n Compatible with TIA/EIA-644 LVDS standard  
n Single pixel per clock XGA (1024 x 768)  
n Supports VGA, SVGA, XGA and higher  
n 1.3 Gbps throughput  
and  
3 bits of LCD timing and control data (FPLINE,  
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per  
LVDS data channel. Using a 65 MHz clock, the data through-  
put is 171 Mbytes per second. These devices are offered  
with falling edge data strobes for convenient interface with a  
variety of graphics and LCD panel controllers.  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
Block Diagrams  
DS90CF563  
DS90CF564  
DS012615-2  
DS012615-1  
Order Number DS90CF563MTD  
See NS Package Number MTD48  
Order Number DS90CF564MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS012615  
www.national.com  

DS90CF564MTD/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90CF564MTDX/NOPB TI

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