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DS90CF562MWC PDF预览

DS90CF562MWC

更新时间: 2024-09-15 20:01:51
品牌 Logo 应用领域
美国国家半导体 - NSC 接口集成电路
页数 文件大小 规格书
17页 316K
描述
IC TRIPLE LINE RECEIVER, UUC, WAFER, Line Driver or Receiver

DS90CF562MWC 技术参数

生命周期:Obsolete包装说明:DIE, WAFER
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:X-XUUC-N
功能数量:3最高工作温度:70 °C
最低工作温度:-10 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:WAFER
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
电源:5 V认证状态:Not Qualified
最大接收延迟:接收器位数:3
子类别:Line Driver or Receivers最大压摆率:80 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

DS90CF562MWC 数据手册

 浏览型号DS90CF562MWC的Datasheet PDF文件第2页浏览型号DS90CF562MWC的Datasheet PDF文件第3页浏览型号DS90CF562MWC的Datasheet PDF文件第4页浏览型号DS90CF562MWC的Datasheet PDF文件第5页浏览型号DS90CF562MWC的Datasheet PDF文件第6页浏览型号DS90CF562MWC的Datasheet PDF文件第7页 
May 1997  
DS90CF561/DS90CF562  
LVDS 18-Bit Color Flat Panel Display (FPD) Link  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
General Description  
The DS90CF561 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CF562 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 40 MHz, 18 bits of RGB data  
and 3 bits of LCD timing and control data (FPLINE, FP-  
FRAME, DRDY) are transmitted at a rate of 280 Mbps per  
LVDS data channel. Using a 40 MHz clock, the data through-  
put is 105 Megabytes per second. These devices are offered  
with falling edge data strobes for convenient interface with a  
variety of graphics and LCD panel controllers.  
Features  
n Up to 105 Megabyte/sec bandwidth  
n Narrow bus reduces cable size and cost  
n 290 mV swing LVDS devices for low EMI  
n Low power CMOS design  
n Power down mode  
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Falling edge data strobe  
n Compatible with TIA/EIA-644 LVDS standard  
Block Diagrams  
DS90CF561  
DS90CF562  
DS012485-26  
DS012485-1  
Order Number DS90CF561MTD  
See NS Package Number MTD48  
Order Number DS90CF562MTD  
See NS Package Number MTD48  
Application  
DS012485-2  
© 2000 National Semiconductor Corporation  
DS012485  
www.national.com  

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