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DS90CF561MTD PDF预览

DS90CF561MTD

更新时间: 2024-09-13 22:40:11
品牌 Logo 应用领域
美国国家半导体 - NSC 显示器接口集成电路光电二极管驱动
页数 文件大小 规格书
12页 248K
描述
LVDS 18-Bit Color Flat Panel Display (FPD) Link

DS90CF561MTD 数据手册

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July 1997  
DS90CF561/DS90CF562  
LVDS 18-Bit Color Flat Panel Display (FPD) Link  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
General Description  
The DS90CF561 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CF562 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 40 MHz, 18 bits of RGB data  
and 3 bits of LCD timing and control data (FPLINE, FP-  
FRAME, DRDY) are transmitted at a rate of 280 Mbps per  
LVDS data channel. Using a 40 MHz clock, the data through-  
put is 105 Megabytes per second. These devices are offered  
with falling edge data strobes for convenient interface with a  
variety of graphics and LCD panel controllers.  
Features  
n Up to 105 Megabyte/sec bandwidth  
n Narrow bus reduces cable size and cost  
n 290 mV swing LVDS devices for low EMI  
n Low power CMOS design  
n Power down mode  
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Falling edge data strobe  
n Compatible with TIA/EIA-644 LVDS standard  
Block Diagrams  
DS90CF561  
DS90CF562  
DS012485-26  
DS012485-1  
Order Number DS90CF561MTD  
See NS Package Number MTD48  
Order Number DS90CF562MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS012485  
www.national.com  

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