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DS90CF388VJDX/NOPB PDF预览

DS90CF388VJDX/NOPB

更新时间： 2024-09-15 11:12:31
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
34页 1236K
描述
+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 接收器 | NEZ | 100 | -10 to 70

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DS90CF388VJDX/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.16
差分输出：YES输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：S-PQFP-G100JESD-609代码：e4
长度：14 mm湿度敏感等级：3
功能数量：8端子数量：100
最高工作温度：70 °C最低工作温度：-10 °C
最小输出摆幅：2.7 V输出特性：DIFFERENTIAL
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：
接收器位数：8座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：300 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

DS90CF388VJDX/NOPB 数据手册

 浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第2页浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第3页浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第4页浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第5页浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第6页浏览型号DS90CF388VJDX/NOPB的Datasheet PDF文件第7页 
DS90C387, DS90CF388  
www.ti.com  
SNLS012H –MAY 2000–REVISED APRIL 2013  
DS90C387, DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA  
Check for Samples: DS90C387, DS90CF388  
1
FEATURES  
DESCRIPTION  
The DS90C387/DS90CF388 transmitter/receiver pair  
2
•
Complies with OpenLDI Specification for  
Digital Display Interfaces  
is designed to support dual pixel data transmission  
between Host and Flat Panel Display up to QXGA  
resolutions. The transmitter converts 48 bits (Dual  
Pixel 24-bit color) of CMOS/TTL data into 8 LVDS  
(Low Voltage Differential Signalling) data streams.  
Control signals (VSYNC, HSYNC, DE and two user-  
defined signals) are sent during blanking intervals. At  
a maximum dual pixel rate of 112MHz, LVDS data  
line speed is 672Mbps, providing a total throughput of  
5.38Gbps (672 Megabytes per second). Two other  
modes are also supported. 24-bit color data (single  
pixel) can be clocked into the transmitter at a  
maximum rate of 170MHz. In this mode, the  
transmitter provides single-to-dual pixel conversion,  
and the output LVDS clock rate is 85MHz maximum.  
The third mode provides inter-operability with FPD-  
Link devices.  
•
•
32.5 to 112/170MHz Clock Support for  
DS90C387, 40 to 112MHz Clock Support for  
DS90CF388  
Supports SVGA through QXGA Panel  
Resolutions  
•
•
•
•
Drives Long, Low Cost Cables  
Up to 5.38Gbps Bandwidth  
Pre-Emphasis Reduces Cable Loading Effects  
DC Balance Data Transmission Provided by  
Transmitter Reduces ISI Distortion  
•
Cable Deskew of +/−1 LVDS Data Bit Time (up  
to 80 MHz Clock Rate) of Pair-to-Pair Skew at  
Receiver Inputs; Intra-Pair Skew Tolerance of  
300ps  
The LDI chipset is improved over prior generations of  
FPD-Link devices and offers higher bandwidth  
support and longer cable drive with three areas of  
enhancement. To increase bandwidth, the maximum  
pixel clock rate is increased to 112 (170) MHz and 8  
serialized LVDS outputs are provided. Cable drive is  
•
Dual Pixel Architecture Supports Interface to  
GUI and Timing Controller; Optional Single  
Pixel Transmitter Inputs Support Single Pixel  
GUI Interface  
•
•
•
Transmitter Rejects Cycle-to-Cycle Jitter  
5V Tolerant on Data and Control Input Pins  
enhanced with  
a user selectable pre-emphasis  
feature that provides additional output current during  
transitions to counteract cable loading effects. DC  
balancing on a cycle-to-cycle basis, is also provided  
to reduce ISI (Inter-Symbol Interference). With pre-  
emphasis and DC balancing, a low distortion eye-  
pattern is provided at the receiver end of the cable. A  
cable deskew capability has been added to deskew  
long cables of pair-to-pair skew of up to +/−1 LVDS  
data bit time (up to 80 MHz Clock Rate). These three  
enhancements allow cables 5+ meters in length to be  
driven. This chipset is an ideal means to solve EMI  
and cable size problems for high-resolution flat panel  
applications. It provides a reliable interface based on  
LVDS technology that delivers the bandwidth needed  
for high-resolution panels while maximizing bit times,  
and keeping clock rates low to reduce EMI and  
shielding requirements. For more details, please refer  
to Applications Information.  
Programmable Transmitter Data and Control  
Strobe Select (Rising or Falling Edge Strobe)  
•
•
•
•
Backward Compatible Configuration Select  
with FPD-Link  
Optional Second LVDS Clock for Backward  
Compatibility w/ FPD-Link  
Support for Two Additional User-Defined  
Control Signals in DC Balanced Mode  
Compatible with ANSI/TIA/EIA-644-1995 LVDS  
Standard  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  
1234567...34

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DS90CF388VJDX/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DS90CF388VJD/NOPB TI

类似代替

 +3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 接收器 | NEZ
DS90CF388AVJD/NOPB TI

类似代替

 双像素 LVDS 显示接口/ FPD 链接接收器 | NEZ | 100 | -10 to

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