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DS90CF388AVJD/NOPB PDF预览

DS90CF388AVJD/NOPB

更新时间: 2024-09-14 19:50:55
品牌 Logo 应用领域
美国国家半导体 - NSC 接口集成电路
页数 文件大小 规格书
19页 797K
描述
IC 9 LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver

DS90CF388AVJD/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TFQFP, TQFP100,.63SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.1差分输出:YES
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3功能数量:9
端子数量:100最高工作温度:70 °C
最低工作温度:-10 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
接收器位数:9座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:14 mmBase Number Matches:1

DS90CF388AVJD/NOPB 数据手册

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February 2006  
DS90C387A/DS90CF388A  
Dual Pixel LVDS Display Interface / FPD-Link  
General Description  
The DS90C387A/DS90CF388A transmitter/receiver pair is  
designed to support dual pixel data transmission between  
Host and Flat Panel Display up to QXGA resolutions. The  
transmitter converts 48 bits (Dual Pixel 24-bit color) of  
CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage  
Differential Signalling) data streams. At a maximum dual  
pixel rate of 112MHz, LVDS data line speed is 784Mbps,  
providing a total throughput of 5.7Gbps (714 Megabytes per  
second).  
vides a reliable interface based on LVDS technology that  
delivers the bandwidth needed for high-resolution panels  
while maximizing bit times, and keeping clock rates low to  
reduce EMI and shielding requirements. For more details,  
please refer to the “Applications Information” section of this  
datasheet.  
Features  
n Supports SVGA through QXGA panel resolutions  
n 32.5 to 112/170MHz clock support  
The LDI chipset is improved over prior generations of FPD-  
Link devices and offers higher bandwidth support and longer  
cable drive. To increase bandwidth, the maximum pixel clock  
rate is increased to 112 MHz and 8 serialized LVDS outputs  
are provided. Cable drive is enhanced with a user selectable  
pre-emphasis feature that provides additional output current  
during transitions to counteract cable loading effects.  
n Drives long, low cost cables  
n Up to 5.7 Gbps bandwidth  
n Pre-emphasis reduces cable loading effects  
n Dual pixel architecture supports interface to GUI and  
timing controller; optional single pixel transmitter inputs  
support single pixel GUI interface  
n Transmitter rejects cycle-to-cycle jitter  
n 5V tolerant on data and control input pins  
n Programmable transmitter data and control strobe select  
(rising or falling edge strobe)  
The DS90C387A transmitter provides a second LVDS output  
clock. Both LVDS clocks are identical. This feature supports  
backward compatibility with the previous generation of FPD-  
Link Receivers - the second clock allows the transmitter to  
interface to panels using a ’dual pixel’ configuration of two  
24-bit or 18-bit FPD-Link receivers.  
n Backward compatible with FPD-Link  
This chipset is an ideal means to solve EMI and cable size  
problems for high-resolution flat panel applications. It pro-  
n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard  
Generalized Transmitter Block Diagram  
10132002  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2006 National Semiconductor Corporation  
DS101320  
www.national.com  

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