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DS90CF388

更新时间： 2024-09-13 22:50:51

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
26页	520K
描述
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

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数据手册

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DS90CF388 数据手册

May 2004

DS90C387/DS90CF388

Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

while maximizing bit times, and keeping clock rates low to

reduce EMI and shielding requirements. For more details,

please refer to the “Applications Information” section of this

datasheet.

General Description

The DS90C387/DS90CF388 transmitter/receiver pair is de-

signed to support dual pixel data transmission between Host

and Flat Panel Display up to QXGA resolutions. The trans-

mitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL

data into 8 LVDS (Low Voltage Differential Signalling) data

streams. Control signals (VSYNC, HSYNC, DE and two

user-defined signals) are sent during blanking intervals. At a

maximum dual pixel rate of 112MHz, LVDS data line speed is

672Mbps, providing a total throughput of 5.38Gbps (672

Megabytes per second). Two other modes are also sup-

ported. 24-bit color data (single pixel) can be clocked into the

transmitter at a maximum rate of 170MHz. In this mode, the

transmitter provides single-to-dual pixel conversion, and the

output LVDS clock rate is 85MHz maximum. The third mode

provides inter-operability with FPD-Link devices.

Features

n Complies with OpenLDI specification for digital display

interfaces

n 32.5 to 112/170MHz clock support for DS90C387, 40 to

112MHz clock support for DS90CF388

n Supports SVGA through QXGA panel resolutions

n Drives long, low cost cables

n Up to 5.38Gbps bandwidth

n Pre-emphasis reduces cable loading effects

n DC Balance data transmission provided by transmitter

reduces ISI distortion

The LDI chipset is improved over prior generations of FPD-

Link devices and offers higher bandwidth support and longer

cable drive with three areas of enhancement. To increase

bandwidth, the maximum pixel clock rate is increased to 112

(170) MHz and 8 serialized LVDS outputs are provided.

n Cable Deskew of +/−1 LVDS data bit time (up to 80

MHz Clock Rate) of pair-to-pair skew at receiver inputs;

intra-pair skew tolerance of 300ps

n Dual pixel architecture supports interface to GUI and

timing controller; optional single pixel transmitter inputs

support single pixel GUI interface

Cable drive is enhanced with

a user selectable pre-

emphasis feature that provides additional output current dur-

ing transitions to counteract cable loading effects. DC bal-

ancing on a cycle-to-cycle basis, is also provided to reduce

ISI (Inter-Symbol Interference). With pre-emphasis and DC

balancing, a low distortion eye-pattern is provided at the

receiver end of the cable. A cable deskew capability has

been added to deskew long cables of pair-to-pair skew of up

to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These

three enhancements allow cables 5+ meters in length to be

driven. This chipset is an ideal means to solve EMI and cable

size problems for high-resolution flat panel applications. It

provides a reliable interface based on LVDS technology that

delivers the bandwidth needed for high-resolution panels

n Transmitter rejects cycle-to-cycle jitter

n 5V tolerant on data and control input pins

n Programmable transmitter data and control strobe select

(rising or falling edge strobe)

n Backward compatible configuration select with FPD-Link

n Optional second LVDS clock for backward compatibility

w/ FPD-Link

n Support for two additional user-defined control signals in

DC Balanced mode

n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100073

www.national.com

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中文翻译

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与DS90CF388相关器件

型号	品牌	获取价格	描述	数据表
DS90CF388A	NSC	获取价格	Dual Pixel LVDS Display Interface / FPD-Link
DS90CF388A	TI	获取价格	双像素 LVDS 显示接口/ FPD 链接接收器
DS90CF388AVJD	NSC	获取价格	Dual Pixel LVDS Display Interface / FPD-Link
DS90CF388AVJD/NOPB	NSC	获取价格	IC 9 LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CF388AVJD/NOPB	TI	获取价格	双像素 LVDS 显示接口/ FPD 链接接收器 \| NEZ \| 100 \| -10 to
DS90CF388VJD	NSC	获取价格	Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
DS90CF388VJD/NOPB	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 接收器 \| NEZ
DS90CF388VJDX	NSC	获取价格	IC 9 LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CF388VJDX/NOPB	NSC	获取价格	IC 9 LINE RECEIVER, PQFP100, TQFP-100, Line Driver or Receiver
DS90CF388VJDX/NOPB	TI	获取价格	+3.3V 双像素 LVDS 显示接口 (LDI)-SVGA/QXGA 接收器 \| NEZ

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