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DS90CF386MTD PDF预览

DS90CF386MTD

更新时间: 2024-09-15 11:13:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管显示器
页数 文件大小 规格书
43页 1983K
描述
+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | DGG | 56 | -10 to 70

DS90CF386MTD 数据手册

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DS90CF366, DS90CF386  
SNLS055J NOVEMBER 1999REVISED MAY 2016  
DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz  
1 Features  
3 Description  
The DS90CF386 receiver converts four LVDS (Low  
Voltage Differential Signaling) data streams back into  
parallel 28 bits of LVCMOS data. Also available is the  
DS90CF366 receiver that converts three LVDS data  
streams back into parallel 21 bits of LVCMOS data.  
The outputs of both receivers strobe on the falling  
edge. A rising edge or falling edge strobe transmitter  
will interoperate with a falling edge strobe receiver  
without any translation logic.  
1
20-MHz to 85-MHz Shift Clock Support  
Rx Power Consumption <142 mW (Typical) at  
85-MHz Grayscale  
Rx Power-Down Mode <1.44 mW (Maximum)  
ESD Rating >7 kV (HBM), >700 V (EIAJ)  
Supports VGA, SVGA, XGA, and Single Pixel  
SXGA  
PLL Requires No External Components  
The receiver LVDS clock operates at rates from  
20 MHz to 85 MHz. The device phase-locks to the  
input LVDS clock, samples the serial bit streams at  
the LVDS data lines, and converts them into parallel  
output data. At an incoming clock rate of 85 MHz,  
each LVDS input line is running at a bit rate of  
595 Mbps, resulting in a maximum throughput of  
2.38 Gbps for the DS90CF386 and 1.785 Gbps for  
the DS90CF366.  
Compatible With TIA/EIA-644 LVDS Standard  
Low Profile 56-Pin or 48-Pin TSSOP Package  
DS90CF386 Also Available in a 64-Pin, 0.8-mm,  
Fine Pitch Ball Grid Array (NFBGA) Package  
2 Applications  
Video Displays  
Printers and Imaging  
Digital Video Transport  
Machine Vision  
The use of these serial link devices is ideal for  
solving EMI and cable size problems associated with  
transmitting data over wide, high-speed parallel  
LVCMOS interfaces. Both devices are offered in  
TSSOP packages. The DS90CF386 is also offered in  
a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA)  
package which provides a 44% reduction in PCB  
footprint compared to the 56-pin TSSOP package.  
Open LDI-to-RGB Bridge  
Device Information(1)  
PART NUMBER  
PACKAGE  
TSSOP (48)  
TSSOP (56)  
NFBGA (64)  
BODY SIZE (NOM)  
12.50 mm × 6.10 mm  
14.00 mm × 6.10 mm  
8.00 mm × 8.00 mm  
DS90CF366  
DS90CF386  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Typical Application Block Diagram (DS90CF366)  
ꢀë5{ /able or ꢂ/. Çrace  
5{90/C366 21-.it wx  
18-.it wD. 5isplay Ünit  
wxhÜÇ[20:0]  
ꢀë5{ 5ata  
100 Q  
Graphics Processor Unit  
(GPU)  
100 Q  
100 Q  
21-Bit Tx Data  
(3 LVDS Data, 1 LVDS Clock)  
ꢀë5{ /lock  
wx/ꢀY  
PLL  
100 Q  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 

DS90CF386MTD 替代型号

型号 品牌 替代类型 描述 数据表
DS90CF386MTDX/NOPB TI

完全替代

+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | D
DS90CF386MTD/NOPB TI

完全替代

+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | D
SN65LVDS94DGGR TI

类似代替

LVDS SERDES RECEIVER

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DS90CF386MTD/NOPB TI

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DS90CF386SLCX/NOPB TI

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+3.3V LVDS 接收器 24 位平板显示器 (FPD) 链路 - 85MHz | N
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Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA