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DS90CF383B

更新时间： 2024-09-15 04:39:11

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器光电二极管
页数	文件大小	规格书
11页	641K
描述
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

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DS90CF383B 数据手册

October 2005

DS90CF383B

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel

Display (FPD) Link-65 MHz

n "Input Clock Detection" feature will pull all LVDS pairs to

logic low when input clock is missing and when /PD pin

General Description

The DS90CF383B transmitter converts 28 bits of CMOS/TTL

is logic high.

data into four LVDS (Low Voltage Differential Signaling) data

streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fifth LVDS link. Every

n 18 to 68 MHz shift clock support

n Best–in–Class Set & Hold Times on TxINPUTs

n Tx power consumption 130 mW (typ) 65MHz

Grayscale

cycle of the transmit clock 28 bits of input data are sampled

and transmitted. At a transmit clock frequency of 65 MHz, 24

bits of RGB data and 3 bits of LCD timing and control data

(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455

Mbps per LVDS data channel. Using a 65 MHz clock, the

data throughput is 227 Mbytes/sec. The DS90CF383B is

fixed as a Falling edge strobe transmitter and will interoper-

ate with a Falling edge strobe Receiver (DS90CF386) with-

out any translation logic.

n 40% Less Power Dissipation than BiCMOS Alternatives

n Tx Power-down mode 60µW (typ)

n Supports VGA, SVGA, XGA and Dual Pixel SXGA.

n Narrow bus reduces cable size and cost

n Up to 1.8 Gbps throughput

n Up to 227 Megabytes/sec bandwidth

n 345 mV (typ) swing LVDS devices for low EMI

n PLL requires no external components

n Compatible with TIA/EIA-644 LVDS standard

n Low profile 56-lead TSSOP package

n Improved replacement for:

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

Features

n No special start-up sequence required between

clock/data and /PD pins. Input signal (clock and data)

can be applied either before or after the device is

powered.

SN75LVDS83, DS90CF383A

n Support Spread Spectrum Clocking up to 100KHz

frequency modulation & deviations of 2.5% center

spread or −5% down spread.

Block Diagram

DS90CF383B

20098501

Order Number DS90CF383BMT

See NS Package Number MTD56

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS200985

www.national.com

12 3 4 5 6 7...11

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与DS90CF383B相关器件

型号	品牌	获取价格	描述	数据表
DS90CF383B_15	TI	获取价格	3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMT	NSC	获取价格	+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMT	TI	获取价格	Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMT/NOPB	TI	获取价格	+3.3V LVDS 发送器 24 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF383BMT-NOPB	TI	获取价格	Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMTX	TI	获取价格	3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMTX/NOPB	TI	获取价格	3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
DS90CF383BMTX/NOPB	NSC	获取价格	IC LINE DRIVER, PDSO56, TSSOP-56, Line Driver or Receiver
DS90CF383MTD	NSC	获取价格	+3.3V LVDS Transmitter 24-Bit Flat Panel Disp
DS90CF383MTD/NOPB	NSC	获取价格	IC LINE DRIVER, PDSO56, PLASTIC, TSSOP-56, Line Driver or Receiver

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