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DS90CF383AMTD PDF预览

DS90CF383AMTD

更新时间: 2024-09-14 22:50:51
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器显示器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
11页 261K
描述
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

DS90CF383AMTD 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:TSSOP-56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.08Is Samacsys:N
差分输出:YES驱动器位数:5
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
功能数量:5端子数量:56
最高工作温度:70 °C最低工作温度:-10 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
最大接收延迟:座面最大高度:1.1 mm
子类别:Line Driver or Receivers最大压摆率:52 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

DS90CF383AMTD 数据手册

 浏览型号DS90CF383AMTD的Datasheet PDF文件第2页浏览型号DS90CF383AMTD的Datasheet PDF文件第3页浏览型号DS90CF383AMTD的Datasheet PDF文件第4页浏览型号DS90CF383AMTD的Datasheet PDF文件第5页浏览型号DS90CF383AMTD的Datasheet PDF文件第6页浏览型号DS90CF383AMTD的Datasheet PDF文件第7页 
July 1998  
DS90C383A/DS90CF383A  
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel  
Display (FPD) Link-65 MHz  
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD)  
Link-65 MHz  
1.0 General Description  
2.0 Features  
n 20 to 65 MHz shift clock support  
The DS90C383A/DS90CF383A transmitter converts 28 bits  
of CMOS/TTL data into four LVDS (Low Voltage Differential  
Signaling) data streams. A phase-locked transmit clock is  
transmitted in parallel with the data streams over a fifth  
LVDS link. Every cycle of the transmit clock 28 bits of input  
data are sampled and transmitted. At a transmit clock fre-  
quency of 65 MHz, 24 bits of RGB data and 3 bits of LCD  
timing and control data (FPLINE, FPFRAME, DRDY) are  
transmitted at a rate of 455 Mbps per LVDS data channel.  
Using a 65 MHz clock, the data throughput is 227 Mbytes/  
sec. The DS90C383A transmitter can be programmed for  
Rising edge strobe or Falling edge strobe through a dedi-  
cated pin. The DS90CF383A is fixed as a Falling edge  
strobe transmitter. A Rising edge or Falling edge strobe  
transmitter will interoperate with a Falling edge strobe Re-  
ceiver (DS90CF384) without any translation logic.  
> ±  
n Rejects  
225ps output Jitter 65MHz (TJCC)  
3ns Jitter from VGA chip with less than  
@
n Best–in–Class Set & Hold Times on TxINPUTs  
n Tx power consumption 130 mW (typ) 65MHz  
Grayscale  
<
@
>
n
50% Less Power Dissipation than BiCMOS  
Alternatives  
n Tx Power-down mode 200µW (max)  
<
>
>
n ESD rating 7 kV (HBM), 500V (EIAJ)  
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.  
n Narrow bus reduces cable size and cost  
n Up to 1.8 Gbps throughput  
n Up to 227 Megabytes/sec bandwidth  
n 345 mV (typ) swing LVDS devices for low EMI  
n PLL requires no external components  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 56-lead TSSOP package  
n Improved replacement for:  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
SN75LVDS83 — DS90C383A  
SN75LVDS81 — DS90CF383A  
3.0 Block Diagrams  
DS90C383A/DS90CF383A  
DS100100-1  
Order Number DS90C383AMTD or DS90CF383AMTD  
See NS Package Number MTD56  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS100100  
www.national.com  

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