Datasheet > DS90CF364A_07

DS90CF364A_07

更新时间： 2024-09-14 04:39:11

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器光电二极管
页数	文件大小	规格书
18页	439K
描述
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65MHz

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DS90CF364A_07 数据手册

July 2007

DS90CF384A/DS90CF364A

+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link

—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display

(FPD) Link—65 MHz

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

General Description

The DS90CF384A receiver converts the four LVDS data

streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec

bandwidth) back into parallel 28 bits of CMOS/TTL data (24

Features

20 to 65 MHz shift clock support

■

bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also

available is the DS90CF364A that converts the three LVDS

data streams (Up to 1.3 Gbps throughput or 170 Megabytes/

sec bandwidth) back into parallel 21 bits of CMOS/TTL data

(18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both

Receivers' outputs are Falling edge strobe. A Rising edge or

Falling edge strobe transmitter (DS90C383A/DS90C363A)

will interoperate with a Falling edge strobe Receiver without

any translation logic.

50% duty cycle on receiver output clock

Best–in–Class Set & Hold Times on RxOUTPUTs

Rx power consumption <142 mW (typ) @65MHz

Grayscale

Rx Power-down mode <200μW (max)

■

ESD rating >7 kV (HBM), >700V (EIAJ)

Supports VGA, SVGA, XGA and Dual Pixel SXGA.

PLL requires no external components

The DS90CF384A / DS90CF364A devices are enhanced

over prior generation receivers and provided a wider data

valid time on the receiver output.

Compatible with TIA/EIA-644 LVDS standard

Low profile 56-lead or 48-lead TSSOP package

The DS90CF384A is also offered in a 64 ball, 0.8mm fine pitch

ball grid array (FBGA) package which provides a 44 % re-

duction in PCB footprint compared to the 56L TSSOP pack-

age.

DS90CF384A is also available in a 64 ball, 0.8mm fine

pitch ball grid array (FBGA) package

Block Diagrams

DS90CF384A

DS90CF364A

10087027

10087028

Order Number DS90CF384AMTD or DS90CF384ASLC

Order Number DS90CF364AMTD

See NS Package Number MTD48

See NS Package Number MTD56 or SLC64A

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

100870

www.national.com

12 3 4 5 6 7...18

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与DS90CF364A_07相关器件

型号	品牌	获取价格	描述	数据表
DS90CF364AMDA	TI	获取价格	暂无描述
DS90CF364AMTD	NSC	获取价格	+3.3V LVDS Receiver 24-Bit Flat Panel Display
DS90CF364AMTD	TI	获取价格	+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF364AMTD/NOPB	TI	获取价格	+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF364AMTDX	TI	获取价格	+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz \| D
DS90CF364AMTDX/NOPB	TI	获取价格	+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz 48-TSSOP -10 to 70
DS90CF364MTD	NSC	获取价格	+3.3V Programmable LVDS Transmitter 18-Bit Fl
DS90CF364MTD/NOPB	NSC	获取价格	IC QUAD LINE RECEIVER, PDSO48, PLASTIC, TSSOP-48, Line Driver or Receiver
DS90CF364MTD/NOPB	TI	获取价格	3.3V Programmable LVDS Transmitter 18-Bit Fla
DS90CF364MTDX	ETC	获取价格	Video Link Interface

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