Datasheet > DS90CF363B_06

DS90CF363B_06

更新时间： 2024-11-02 04:39:11

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器光电二极管
页数	文件大小	规格书
11页	613K
描述
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz

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DS90CF363B_06 数据手册

October 2006

DS90CF363B

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel

Display (FPD) Link -65 MHz

n "Input Clock Detection" feature will pull all LVDS pairs to

logic low when input clock is missing and when /PD pin

General Description

The DS90CF363B transmitter converts 21 bits of CMOS/TTL

is logic high.

data into three LVDS (Low Voltage Differential Signaling)

data streams. A phase-locked transmit clock is transmitted in

parallel with the data streams over a fourth LVDS link. Every

n 18 to 68 MHz shift clock support

n Best–in–Class Set & Hold Times on TxINPUTs

n Tx power consumption 130 mW (typ) 65MHz

Grayscale

cycle of the transmit clock 21 bits of input data are sampled

and transmitted. At a transmit clock frequency of 65 MHz, 18

bits of RGB data and 3 bits of LCD timing and control data

(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455

Mbps per LVDS data channel. Using a 65 MHz clock, the

data throughput is 170 Mbytes/sec. The DS90CF363B is

fixed as a Falling edge strobe transmitter and will interoper-

ate with a Falling edge strobe Receiver (DS90CF366) with-

out any translation logic.

n 40% Less Power Dissipation than BiCMOS Alternatives

n Tx Power-down mode 37µW (typ)

n Supports VGA, SVGA, XGA and Dual Pixel SXGA.

n Narrow bus reduces cable size and cost

n Up to 1.3 Gbps throughput

n Up to 170 Megabytes/sec bandwidth

n 345 mV (typ) swing LVDS devices for low EMI

n PLL requires no external components

n Compatible with TIA/EIA-644 LVDS standard

n Low profile 48-lead TSSOP package

n Improved replacement for:

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

Features

n No special start-up sequence required between

clock/data and /PD pins. Input signal (clock and data)

can be applied either before or after the device is

powered.

SN75LVDS84, DS90CF363A

n Support Spread Spectrum Clocking up to 100KHz

frequency modulation & deviations of 2.5% center

spread or −5% down spread.

Block Diagram

DS90CF363B

20098701

Order Number DS90CF363BMT

See NS Package Number MTD48

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS200987

www.national.com

12 3 4 5 6 7...11

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与DS90CF363B_06相关器件

型号	品牌	获取价格	描述	数据表
DS90CF363BMT	NSC	获取价格	+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz
DS90CF363BMT	TI	获取价格	3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
DS90CF363BMT/NOPB	TI	获取价格	+3.3V 下降沿 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz
DS90CF363BMTX	TI	获取价格	3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
DS90CF363BMTX/NOPB	TI	获取价格	+3.3V 下降沿 LVDS 发送器 18 位平板显示器 (FPD) 链路 - 65MHz
DS90CF363MDC	NSC	获取价格	暂无描述
DS90CF363MTD	NSC	获取价格	+3.3V LVDS Transmitter 18-Bit Flat Panel Disp
DS90CF363MTDX	NSC	获取价格	IC TRIPLE LINE DRIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48, Line Driver or Receiver
DS90CF364	NSC	获取价格	+3.3V LVDS Receiver 24-Bit Flat Panel Display
DS90CF364	TI	获取价格	+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 65MHz

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