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DS90C365A

更新时间： 2024-02-15 20:17:10
品牌 Logo 应用领域
德州仪器 - TI 显示器
页数 文件大小 规格书
16页 918K
描述
3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

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DS90C365A 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP48,.3,20Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.11差分输出：YES
驱动器位数：4输入特性：STANDARD
接口集成电路类型：LINE DRIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：12.5 mm功能数量：4
端子数量：48最高工作温度：70 °C
最低工作温度：-10 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.2 mm子类别：Line Driver or Receivers
最大压摆率：57 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

DS90C365A 数据手册

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DS90C365A  
www.ti.com  
SNLS181I –APRIL 2004–REVISED APRIL 2013  
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz  
Check for Samples: DS90C365A  
1
FEATURES  
DESCRIPTION  
The DS90C365A is  
a
pin to pin compatible  
23  
•
Pin-to-pin compatible to DS90C363,  
DS90C363A and DS90C365  
replacement for DS90C363, DS90C363A and  
DS90C365. The DS90C365A has additional features  
and improvements making it an ideal replacement for  
DS90C363, DS90C363A and DS90C365. family of  
LVDS Transmitters.  
•
No special start-up sequence required  
between clock/data and /PD pins. Input signals  
(clock and data) can be applied either before  
or after the device is powered.  
The DS90C365A transmitter converts 21 bits of  
LVCMOS/LVTTL data into four LVDS (Low Voltage  
Differential Signaling) data streams. A phase-locked  
transmit clock is transmitted in parallel with the data  
streams over the fourth LVDS link. Every cycle of the  
transmit clock 21 bits RGB of input data are sampled  
and transmitted. At a transmit clock frequency of 87.5  
MHz, 21 bits of RGB data and 3 bits of LCD timing  
and control data (FPLINE, FPFRAME, DRDY) are  
transmitted at a rate of 612.5 Mbps per LVDS data  
channel. Using a 87.5 MHz clock, the data throughput  
is 229.687 Mbytes/sec. This transmitter can be  
programmed for Rising edge strobe or Falling edge  
strobe through a dedicated pin. A Rising edge or  
Falling edge strobe transmitter will interoperate with a  
Falling edge strobe FPDLink Receiver without any  
translation logic.  
•
•
Support Spread Spectrum Clocking up to  
100kHz frequency modulation & deviations of  
±2.5% center spread or -5% down spread.  
“Input Clock Detection” feature will pull all  
LVDS pairs to logic low when input clock is  
missing and when /PD pin is logic high.  
•
•
18 to 87.5 MHz shift clock support  
Tx power consumption < 146 mW (typ) at 87.5  
MHz Grayscale  
•
•
Tx Power-down mode < 37 uW (typ)  
Supports VGA, SVGA, XGA, SXGA (dual pixel),  
SXGA+ (dual pixel), UXGA (dual pixel).  
•
•
•
•
•
•
•
Narrow bus reduces cable size and cost  
Up to 1.785 Gbps throughput  
This chipset is an ideal means to solve EMI and  
cable size problems associated with wide, high-speed  
TTL interfaces with added Spead Spectrum Clocking  
support..  
Up to 223.125 Megabytes/sec bandwidth  
345 mV (typ) swing LVDS devices for low EMI  
PLL requires no external components  
Compliant to TIA/EIA-644 LVDS standard  
Low profile 48-lead TSSOP package  
Block Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
TRI-STATE is a registered trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2013, Texas Instruments Incorporated  
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