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DS90C3201 PDF预览

DS90C3201

更新时间: 2024-02-15 04:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管
页数 文件大小 规格书
3页 484K
描述
3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TFQFP, TQFP128,.63SQ,16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.85接口集成电路类型:BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码:S-PQFP-G128JESD-609代码:e3
长度:14 mm湿度敏感等级:3
端子数量:128最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP128,.63SQ,16
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Line Driver or Receivers最大压摆率:235 mA
标称供电电压:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

DS90C3201 数据手册

 浏览型号DS90C3201的Datasheet PDF文件第2页浏览型号DS90C3201的Datasheet PDF文件第3页 
ADVANCE INFORMATION  
April 2005  
DS90C3201  
3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter  
General Description  
Features  
n Up to 9.45Gbit/s data throughput  
n 8 MHz to 135 MHz input clock support  
n Supports up to QXGA panel resolutions  
n Supports HDTV resolutions and frame rates up to  
1920 x 1080p  
The DS90C3201 is a 3.3V single/dual FPD-Link 10-bit color  
transmitter is designed to be used in Liquid Crystal Display  
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel  
TVs. The DS90C3201 is designed to interface between the  
digital video processor and the display device using the  
low-power, low-EMI LVDS (Low Voltage Differential Signal-  
ing) interface. The DS90C3201 converts up to 70 bits of  
LVCMOS/LVTTL data into ten LVDS data streams. The  
transmitter can be programmed clocking data with rising  
edge or falling edge clock. Optional two-wire serial program-  
ming allows fine tuning in development and production en-  
vironments. At a transmitted clock frequency of 135 MHz, 70  
bits of LVCMOS/LVTTL data are transmitted at an effective  
rate of 945 Mbps per LVDS channel. Using a 135 MHz clock,  
the data throughput is 9.45Gbit/s (945Mbytes/s). This allows  
the dual 10-bit LVDS Transmitter to support HDTV resolu-  
tions.  
n LVDS 30-bit, 24-bit or 18-bit color data outputs  
n Supports single pixel and dual pixel interfaces  
n Supports spread spectrum clocking  
n Two-wire serial communication interface  
n Programmable clock edge and control strobe select  
n Power down mode  
n +3.3V supply voltage  
n 128-pin TQFP  
n Compliant to TIA/EIA-644-A-2001 LVDS Standard  
n Backward compatible configuration with FPD-Link  
Block Diagram  
20147201  
FIGURE 1. Transmitter Block Diagram  
© 2005 National Semiconductor Corporation  
DS201472  
www.national.com  

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