Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90C2501SLB

DS90C2501SLB

更新时间： 2024-01-21 01:10:47

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
48页	644K
描述
Transmitter with built-in scaler for LVDS Display Interface (LDI)

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技术参数
数据手册

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DS90C2501SLB 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QCCN, LGA128,20X20,20	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
差分输出：	NO	驱动器位数：	2
输入特性：	STANDARD	接口集成电路类型：	LINE DRIVER
接口标准：	EIA-644; TIA-644	JESD-30 代码：	S-XQCC-N128
长度：	10 mm	功能数量：	2
端子数量：	128	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	UNSPECIFIED
封装代码：	QCCN	封装等效代码：	LGA128,20X20,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5,3.3 V
认证状态：	Not Qualified	最大接收延迟：
座面最大高度：	1.1 mm	子类别：	Line Driver or Receivers
最大供电电压：	2.75 V	最小供电电压：	2.25 V
标称供电电压：	2.5 V	电源电压1-最大：	3.6 V
电源电压1-分钟：	3 V	电源电压1-Nom：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10 mm
Base Number Matches：	1

DS90C2501SLB 数据手册

October 2003

DS90C2501

Transmitter with built-in scaler for LVDS Display

Interface (LDI)

General Description

Features

n Complies with Open LDI and GMCH DVO specification

for digital display interfaces

The DS90C2501 is a highly integrated scaling IC with LVDS

transmitter with a scaled resolution up to SXGA+ for single

pixel input. The DS90C2501 is a video controller hub de-

signed to be compatible with Graphic Memory Controller

Hub (GMCH). The input interface can be single or dual DVO

port (12 pin per port). The high quality cubic zoom engine

scales the input graphics into the desired/optimal output

resolution up to 1400x1050 resolution. Advanced video digi-

tal signal processing provides gamma correction, and dith-

ering for the display output. A two-wire serial interface is

used to communicate with the host system. The dual high

speed LVDS channels supports single pixel in-single pixel

out, single pixel in-dual pixel out, and dual pixel in-dual pixel

out transmission modes. The DS90C2501 complies to Open

LDI standard, and can be paired up with DS90CF388 re-

ceiver or FPD8531x/FPD8731x series integrated timing con-

troller or FPDLink LVDS receivers such as DS90CF364/

DS90CF384A/DS90CF384/DS90CF384A. The LVDS output

is similar to DS90C387 and DS90C387R. Thus, this trans-

mitter can be paired up with DS90CF388, receiver of

112MHz LDI chipset or FPD-Link Receivers in non-DC Bal-

ance mode operation which provides GUI/LCD panel/mother

board vendors a wide choice of inter-operation with LVDS

based TFT panels.

n 25 to 65 MHz clock in single pixel in to single pixel out

operation.

n 50 to 130 MHz clock in single pixel in to dual pixel out

operation.

n Support 24bit/48bit color TFT LCD with Conventional

and Non-Conventional Color Mappings.

n Support 16bit/32bit color TFT LCD.

n Single pixel transmitter inputs support single pixel GUI

interface.

n Up scaling/panel fitting supports VGA to SXGA+ output

in single pixel input mode at 640x480 60Hz,

800x600 60Hz, 1024x768 60Hz, 1280x1024 60Hz,

1400x1050 60Hz.

n Independent horizontal and vertical scaling.

n Support dithering (available for 6-bit color only),

programmable smoothing and anti-aliasing filter.

n Programmable digital sharpness, edge enhancement

and contrast control via gamma correction.

n Allow 2% at 200KHz spread spectrum clocking, rejects

cycle-to-cycle jitter (+/− 20% of input data bit time).

n Programmable LCD panel power sequencing.

n Support low voltage swing signal level (1V to 1.8V),

2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to

D23, DE, HSYNC and VSYNC pins

n Support 2.5V/3.3V LVTTL level on configuration pins

n Support 3.3V LVTTL level on GPIO pins

n Available in 10mm x 10mm x 1mm 128pin thermally

enhanced CSP package.

n Two-wire serial communication interface is active during

normal as well as power down mode and support data

rates up to 400KHz.

This chip is an ideal solution to solve EMI and cable size

problems for high-resolution flat panel applications. It pro-

vides a reliable industry standard interface based on LVDS

technology that delivers the bandwidth needed for high-

resolution panels while maximizing bit times, and keeping

clock rates low to reduce EMI and shielding requirements.

For more details, please refer to the “Applications Informa-

tion” section of this datasheet.

n TIA/EIA-644, Open LDI, DVO compliance.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DVO is a registered trademark of Intel Corporation.

AGP or 4x AGP is a registered trademark of Intel Corporation.

DS200045

www.national.com

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与DS90C2501SLB相关器件

型号	品牌	获取价格	描述	数据表
DS90C2501SLBX	NSC	获取价格	IC DUAL LINE DRIVER, QCC128, 10 X 10 MM, 1 MM HEIGHT, CSP-128, Line Driver or Receiver
DS90C3201	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
DS90C3201	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接发送器
DS90C3201_06	NSC	获取价格	3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter
DS90C3201VS	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
DS90C3201VS/NOPB	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接发送器 \| PDT \| 128 \|
DS90C3202	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
DS90C3202	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接接收器
DS90C3202VS	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
DS90C3202VS/NOPB	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接接收器 \| PDT \| 128 \|

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