Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90C241QVSX

DS90C241QVSX

更新时间： 2024-01-07 07:08:30

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
26页	1040K
描述
5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS90C241QVSX 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84

DS90C241QVSX 数据手册

January 8, 2008

DS90C241/DS90C124

5-35MHz DC-Balanced 24-Bit LVDS Serializer and

Deserializer

General Description

The DS90C241/DS90C124 Chipset translates a 24-bit paral-

lel bus into a fully transparent data/control LVDS serial stream

with embedded clock information. This single serial stream

simplifies transferring a 24-bit bus over PCB traces and cable

by eliminating the skew problems between parallel data and

clock paths. It saves system cost by narrowing data paths that

in turn reduce PCB layers, cable width, and connector size

and pins.

User selectable clock edge for parallel data on both

Transmitter and Receiver

Internal DC Balancing encode/decode – Supports AC-

coupling interface with no external coding required

Individual power-down controls for both Transmitter and

Receiver

Embedded clock CDR (clock and data recovery) on

Receiver and no external source of reference clock

needed

All codes RDL (random data lock) to support live-

pluggable applications

■

The DS90C241/DS90C124 incorporates LVDS signaling on

the high-speed I/O. LVDS provides a low power and low noise

environment for reliably transferring data over a serial trans-

mission path. By optimizing the serializer output edge rate for

the operating frequency range EMI is further reduced.

LOCK output flag to ensure data integrity at Receiver side

■

Balanced T_SETUP/T_HOLDbetween RCLK and RDATA on

Receiver side

PTO (progressive turn-on) LVCMOS outputs to reduce

EMI and minimize SSO effects

All LVCMOS inputs and control pins have internal

pulldown

■

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding/decoding is used to support AC-Coupled

interconnects.

On-chip filters for PLLs on Transmitter and Receiver

Temperature range –40°C to +105°C

Greater than 8 kV HBM ESD tolerant

Meets AEC-Q100 compliance

■

Features

5 MHz–35 MHz clock embedded and DC-Balancing 24:1

■

and 1:24 data transmissions

User defined Pre-Emphasis driving ability through external

resistor on LVDS outputs and capable to drive up to 10

meters shielded twisted-pair cable

Power supply range 3.3V ± 10%

48-pin TQFP package

■

Block Diagram

20171901

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

201719

www.national.com

12 3 4 5 6 7...26

中文翻译

下载PDF

与DS90C241QVSX相关器件

型号	品牌	获取价格	描述	数据表
DS90C241QVSX/NOPB	TI	获取价格	5MHz 至 35MHz 直流平衡 24 位汽车类 FPD-Link II 串行器 \| P
DS90C2501	NSC	获取价格	Transmitter with built-in scaler for LVDS Display Interface (LDI)
DS90C2501SLB	NSC	获取价格	Transmitter with built-in scaler for LVDS Display Interface (LDI)
DS90C2501SLBX	NSC	获取价格	IC DUAL LINE DRIVER, QCC128, 10 X 10 MM, 1 MM HEIGHT, CSP-128, Line Driver or Receiver
DS90C3201	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
DS90C3201	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接发送器
DS90C3201_06	NSC	获取价格	3.3V 8 MHz to 135MHz Dual FPD-LIink Transmitter
DS90C3201VS	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
DS90C3201VS/NOPB	TI	获取价格	3.3V 8MHz 至 135MHz 双路 FPD 链接发送器 \| PDT \| 128 \|
DS90C3202	NSC	获取价格	3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

与DS90C241QVSX相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

4
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

4
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

4
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

5

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90C241QVSX

DS90C241QVSX 技术参数

DS90C241QVSX 数据手册

与DS90C241QVSX相关器件

与DS90C241QVSX相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS90C241QVSX

DS90C241QVSX 技术参数

DS90C241QVSX 数据手册

与DS90C241QVSX相关器件

与DS90C241QVSX相关文章

您还可以找

您在本页遇到什么问题？