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DS8836

更新时间： 2024-11-01 04:15:19

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
4页	105K
描述
Quad NOR Unified Bus Receiver

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DS8836 数据手册

February 1996

DS7836/DS8836 Quad NOR Unified Bus Receiver

General Description

Features

Low input current with normal

(15 mA typ)

The DS7836/DS8836 are quad 2-input receivers designed

for use in bus organized data transmission systems inter-

connected by terminated 120X impedance lines. The exter-

nal termination is intended to be 180X resistor from the bus

Built-in input hysteresis (1V typ)

High noise immunity (2V typ)

to the 5V logic supply together with a 390X resistor from

Temperature-insensitive input thresholds track bus logic

levels

the bus to ground. The design employs a built-in input hys-

teresis providing substantial noise immunity. Low input cur-

rent allows up to 27 driver/receiver pairs to utilize a com-

mon bus. Performance is optimized for systems with bus

TTL compatible output

Matched, optimized noise immunity for ‘‘1’’ and ‘‘0’’

levels

rise and fall times

1.0 ms/V.

High speed (18 ns typ)

Typical Application

120X Unified Data Bus

TL/F/5810–1

Connection Diagram

Dual-In-Line Package

TL/F/5810–2

Top View

Order Number DS7836J or DS8836N

See NS Package Number J14A or N14A

1996 National Semiconductor Corporation

TL/F/5810

RRD-B30M36/Printed in U. S. A.

http://www.national.com

12 3 4

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与DS8836相关器件

型号	品牌	获取价格	描述	数据表
DS8836J	ETC	获取价格	Quad 2-input NOR Gate
DS8836J/A+	ETC	获取价格	Quad 2-input NOR Gate
DS8836N	NSC	获取价格	Quad NOR Unified Bus Receiver
DS8836N/A+	ETC	获取价格	Quad 2-input NOR Gate
DS8836N/B+	ETC	获取价格	Quad 2-input NOR Gate
DS8837	NSC	获取价格	Hex Unified Bus Receiver
DS8837J	ETC	获取价格	Line Receiver
DS8837J/A+	ETC	获取价格	Line Receiver
DS8837M	NSC	获取价格	Hex Unified Bus Receiver
DS8837M	TI	获取价格	DUAL LINE RECEIVER, PDSO16, 0.150 INCH, PLASTIC, SOP-16