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DS8614N-2 PDF预览

DS8614N-2

更新时间: 2024-11-24 19:56:55
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 110K
描述
IC DS86 SERIES, PRESCALER, PDIP8, PLASTIC, DIP-8, Prescaler/Multivibrator

DS8614N-2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP8,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N其他特性:EITHER TOTEM POLE OR OPEN-COLLECTOR OUTPUT IS AVAILABLE
系列:DS86JESD-30 代码:R-PDIP-T8
JESD-609代码:e0长度:9.817 mm
逻辑集成电路类型:PRESCALER最大频率@ Nom-Sup:225000000 Hz
数据/时钟输入次数:1功能数量:1
端子数量:8最高工作温度:70 °C
最低工作温度:-30 °C输出特性:OPEN-COLLECTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

DS8614N-2 数据手册

 浏览型号DS8614N-2的Datasheet PDF文件第2页浏览型号DS8614N-2的Datasheet PDF文件第3页浏览型号DS8614N-2的Datasheet PDF文件第4页浏览型号DS8614N-2的Datasheet PDF文件第5页浏览型号DS8614N-2的Datasheet PDF文件第6页 
July 1992  
DS8615/DS8616 130/225 MHz  
Low Power Dual Modulus Prescalers  
General Description  
The DS8615 series products are low power dual modulus  
prescalers which divide by 32/33 and 40/41 respectively.  
The modulus control (MC) input selects division by N when  
The device can be used in phase-locked loop applications  
such as FM radio or other communications bands to pre-  
scale the input frequency down to a more usable level. A  
digital frequency display system can also be derived sepa-  
rately or in conjunction with a phase-locked loop, and it can  
extend the useful range of many inexpensive frequency  
counters to 225 MHz.  
a
at a high TTL level and division by N  
1 when at a low TTL  
level. The clock inputs are buffered, providing 40/100  
mVrms input sensitivity. The two outputs provide the user  
the option to wire either a totem-pole or open-collector out-  
put structure. Additionally, the user can wire a resistor be-  
tween the two output pins to minimize edge transition emis-  
sions. The outputs are designed to drive positive edge trig-  
gered PLLs. These products can be operated from either an  
Features  
Y
Input frequency: 130 MHz (-4); 225 MHz (-2)  
Y
Low power: 10 mA (-4, -2)  
g
unregulated 5.5V to 13.5V source or regulated 5V 10%  
source. Unregulated operation is obtained by connecting V  
Y
Input sensitivity: 100 mVrms (-4); 40 mVrms (-2)  
S
Y
Pin compatible with Motorola MC12015-16 prescalers  
to the source with V  
open. Regulated operation is ob-  
to the supply  
REG  
Y
Unregulated/regulated power supply option  
tained by connecting both V and V  
S
source.  
REG  
Logic and Connection Diagrams  
d
a
1
Generalized  
N/N  
TL/F/5240–1  
Dual-In-Line Package  
TL/F/5240–2  
Top View  
Order Number DS8615N or DS8616N (-4, -2)  
See NS Package Number N08E  
C
1995 National Semiconductor Corporation  
TL/F/5240  
RRD-B30M105/Printed in U. S. A.  

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