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DS5240F-1N5 PDF预览

DS5240F-1N5

更新时间: 2024-11-17 22:15:07
品牌 Logo 应用领域
达拉斯 - DALLAS 微控制器和处理器
页数 文件大小 规格书
3页 47K
描述
High-Speed Secure Microcontroller

DS5240F-1N5 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.75Base Number Matches:1

DS5240F-1N5 数据手册

 浏览型号DS5240F-1N5的Datasheet PDF文件第2页浏览型号DS5240F-1N5的Datasheet PDF文件第3页 
An NDA is required for full disclosure of details. Contact factory.  
DS5240  
High-Speed Secure Microcontroller  
www.maxim-ic.com  
FEATURES  
§
Security features  
§
-
Advanced features  
CRC-16/32 generator provides strong error  
detection of memory contents  
-
Designed to meet the physical security requirements  
of FIPS140 and Common Criteria certifications  
Fine-line, top-level metal pattern detects intrusion of  
the chip’s cryptographic boundary  
Additional on-chip sensors detect out-of-range  
environmental conditions that generate a tamper  
response  
-
-
-
-
True-time clock with alarm interrupt and wake-up  
5kB internal SRAM with 1kB that can be allocated  
to a stack for high-level language support  
Programmable length MOVX instructions allow a  
combination of fast and slow devices  
On-chip power detection/selection circuits provide  
power-up/down processor reset and early-warning  
power-fail interrupt  
-
-
-
-
The equipment enclosure can be monitored by  
tamper response inputs for added protection  
Fast write SRAM technology causes rapid  
“zeroization” of secure information as a tamper  
response  
-
§
-
-
-
Watchdog timer  
Proven 4-clock/machine cycle architecture  
Single-cycle instruction executes in 160ns  
Runs up to 25MHz clock rates  
Dual data pointers can increment or decrement  
independently  
-
Eavesdropping on the external memory bus  
prevented by single or triple-DES encryption of the  
programs  
-
-
-
Internal chip clock isolated from external system  
clock by phase-locked loop  
Asynchronous internal ring oscillator provides clock  
for arithmetic operations  
-
Automatic data pointer selection available  
51  
80  
Resources inside cryptographic boundary include:  
81  
50  
-
Modulo Arithmetic Accelerator (MAA) for up to  
4096-bit (e.g., PKI)  
-
DES and 112-bit key triple-DES engines  
available for secret key cryptography  
Random number generator  
Memory Management Unit and 1kB cache  
Firmware bootstrap loader resides in a 16kB  
factory-programmed ROM  
DS5240  
(Top View)  
-
-
-
31  
100  
1
30  
100-pin QFP  
§
-
8051 compatible with expanded addressing  
Linear address space directly accesses up to 8MB  
of external memory  
64  
41  
40  
-
-
Dedicated memory and parallel I/O bus saves port  
pins  
Four 8-bit ports, one 6-bit port  
65  
DS5240  
(Top View)  
25  
80  
24  
1
80-pin QFP  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple  
revisions of any device may be simultaneously available through various sales channels. For information about DS5240 device  
errata, contact the factory.  
1 of 3  
041802  

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