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DS40MB200SQ PDF预览

DS40MB200SQ

更新时间: 2024-11-23 20:26:35
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
20页 927K
描述
Dual 4.0 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization 48-WQFN -40 to 85

DS40MB200SQ 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:not_compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:8.25其他特性:1:2 FANOUT BUFFER AVAILABLE
系列:DS40JESD-30 代码:S-XQCC-N48
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:MULTIPLEXER湿度敏感等级:3
功能数量:2输入次数:2
输出次数:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):2 ns认证状态:Not Qualified
座面最大高度:0.8 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.13 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

DS40MB200SQ 数据手册

 浏览型号DS40MB200SQ的Datasheet PDF文件第2页浏览型号DS40MB200SQ的Datasheet PDF文件第3页浏览型号DS40MB200SQ的Datasheet PDF文件第4页浏览型号DS40MB200SQ的Datasheet PDF文件第5页浏览型号DS40MB200SQ的Datasheet PDF文件第6页浏览型号DS40MB200SQ的Datasheet PDF文件第7页 
DS40MB200  
www.ti.com  
SNLS144I JUNE 2005REVISED MARCH 2013  
DS40MB200 Dual 4.0 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and  
Receive Equalization  
Check for Samples: DS40MB200  
1
FEATURES  
DESCRIPTION  
The DS40MB200 is a dual signal conditioning 2:1  
multiplexer and 1:2 fan-out buffer designed for use in  
2
1– 4 Gbps Low Jitter Operation  
Fixed Input Equalization  
backplane  
redundancy  
applications.  
Signal  
Programmable Output Pre-Emphasis  
conditioning features include input equalization and  
programmable output pre-emphasis that enable data  
communication in FR4 backplanes up to 4 Gbps.  
Each input stage has a fixed equalizer to reduce ISI  
distortion from board traces.  
Independent Switch and Line Side Pre-  
Emphasis Controls  
Programmable Switch-Side Loopback Mode  
On-Chip Terminations  
All output drivers have 4 selectable steps of pre-  
emphasis to compensate for transmission losses from  
long FR4 backplanes and reduce deterministic jitter.  
The pre-emphasis levels can be independently  
controlled for the line-side and switch-side drivers.  
The internal loopback paths from switch-side input to  
switch-side output enable at-speed system testing. All  
receiver inputs are internally terminated with 100  
differential terminating resistors. All drivers are  
+3.3V Supply  
ESD Rating HBM 6 kV  
Lead-Less WQFN-48 Package (7 mm x 7 mm)  
0°C to +85°C Operating Temperature Range  
APPLICATIONS  
Backplane or Cable Driver  
internally terminated with 50to VCC  
.
Redundancy and Signal Conditioning  
Applications  
XAUI  
Functional Block Diagram  
SIA_0 ±  
SIB_0 ±  
EQ  
EQ  
LO_0 ±  
PRE_L  
MUX_S0  
LB0A  
Port 0  
SOA_0 ±  
PRE_S  
SOB_0 ±  
LB0B  
LI_0 ±  
EQ  
PRE_S  
SIA_1 ±  
SIB_1 ±  
EQ  
LO_1 ±  
PRE_L  
MUX_S1  
EQ  
LB1A  
Port 1  
SOA_1 ±  
PRE_S  
SOB_1 ±  
LB1B  
LI_1 ±  
EQ  
PRE_S  
PreL_0  
PreL_1  
V
PRE_L  
PRE_S  
CC  
Pre-emphasis  
Control  
PreS_0  
PreS_1  
GND  
RSV  
All CML inputs and outputs must be AC coupled for optimal performance.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  

DS40MB200SQ 替代型号

型号 品牌 替代类型 描述 数据表
DS40MB200SQ/NOPB TI

完全替代

Dual 4-Gbps 2:1/1:2 CML MUX/Buffer

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