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DS3875W/883 PDF预览

DS3875W/883

更新时间： 2024-11-23 21:22:15
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟外围集成电路
页数 文件大小 规格书
10页 123K
描述
IC 40 MHz, BUS ARBITER AND CONT SIG GEN, CQFP68, CQD-68, System Interface Logic

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中文翻译

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DS3875W/883 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QFF, QFL68,.95SQReach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.31.00.01
风险等级：5.73最大时钟频率：40 MHz
JESD-30 代码：S-GQFP-F68JESD-609代码：e0
长度：22.15 mm端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：QFF
封装等效代码：QFL68,.95SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：4.06 mm
子类别：System Interface Logic最大压摆率：100 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：22.15 mm
uPs/uCs/外围集成电路类型：SYSTEM INTERFACE LOGIC, BUS ARBITER AND CONTINUOUS SIGNAL GENERATORBase Number Matches：1

DS3875W/883 数据手册

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PRELIMINARY  
March 1994  
a
DS3875 Futurebus Arbitration Controller MIL-STD-883  
General Description  
Y
(For a complete description of operation, please refer to the commercial  
User programmable 16 arbitration delays (8 slow and  
datasheet.)  
8 fast)  
a
The DS3875 Futurebus Arbitration Controller is a member  
of National Semiconductor’s Futurebus chip set designed  
Y
Built-in PLL for accurate delays. The PLL accepts  
clocks from 2 MHz to 40 MHz in steps of 1 MHz  
Signal to unlock slave modules on transfer of tenure.  
Auto unlock through a dummy cycle if the current mas-  
ter locked resources  
a
a
specifically for the IEEE 896.1 Futurebus standard. The  
Y
Y
DS3875 implements Distributed Arbitration and Distributed  
Arbitration messages in a single chip.  
a
The DS3875 interfaces with Futurebus  
through the  
Programmable delay for releasing ar* after issuing  
DS3885 BTL Arbitration Transceiver and the DS3884A BTL  
Handshake Transceiver. The DS3885 BTL Arbitration  
Transceiver incorporates the competition logic needed for  
the Arbitration Number signal lines. The DS3884A BTL  
Handshake Transceiver has selectable Wired-OR receiver  
glitch filtering. The DS3884A is used for the Arbitration Se-  
quencing and Arbitration Condition signal lines.  
COMPETE/IBA CMPT. This is to ensure the assertion  
Ð
of the arbitration number during competition, before the  
release of ar*. Also this delay ensures there is suffi-  
cient time to assert the AD/DATA lines during Idle Bus  
Arbitration before the release of ar*  
Read/Write facility with data acknowledge for the host  
to load arbitration numbers, an arbitration message,  
and control registers  
Y
a
Additional transceiver included in the military Futurebus  
Y
Y
chip set is the DS3886A BTL 9-bit Latching Data Transceiv-  
er. The DS3886A transceiver features edge-triggered latch-  
es in the driver which may be bypassed during a fall-through  
mode and a transparent latch in the receiver.  
On chip parity generator unloads the host of the addi-  
tional parity generation function  
Separate interrupts to indicate error occurrence and ar-  
bitration message received. Interrupts cleared on a reg-  
ister write. Error status is available in a separate status  
register  
a
The Logical Interface Futurebus Engine (LIFE) I/O Proto-  
col Controller with 64-bit Data Path incorporates the Com-  
a
Controller handles all the handshaking signals between the  
a
Futurebus and the local bus interfaces, and incorporates  
a DMA Controller with built-in FIFOs for fast queueing.  
Y
Y
Y
pelled Mode Futurebus  
Parallel Protocol. The Protocol  
A
special output pin to indicate that  
message was received  
a POWERFAIL  
Hardwired register to hold the first word of the arbitra-  
tion message  
FIFO strobe provided to store more than one arbitration  
message externally to prevent overrun  
Idle Bus Arbitration (IBA) supported  
Features  
Y
The controller implements the complete requirements  
of the IEEE 896.1 specification as a subset of its fea-  
tures  
Y
Y
Y
Parking implemented  
Bus initialization, system reset and Live-insertion sup-  
ported. (The logic to detect these conditions must be  
implemented externally.)  
Y
Supports Arbitration message sending and receiving  
Y
Supports the two modes of operation (RESTRICTED/  
UNRESTRICTED)  
Y
Y
Testability in the form of reading from key registers  
which include the STATE, MCW, 1 ms timer and pro-  
grammable input clock divider  
Y
Software configurable double/single pass operation,  
slow/fast, IBA/Parking and restricted/unrestricted  
modes of arbitration  
68-pin CQD Package  
Y
Built-in 1 ms timer for use in the arbitration cycle  
TL/F/11977–1  
a
National’s Futurebus Chip Set Diagram  
C
1995 National Semiconductor Corporation  
TL/F/11977  
RRD-B30M105/Printed in U. S. A.  
1234567...10

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