Datasheet > DS3875

DS3875

更新时间： 2024-11-22 22:40:39

品牌	Logo	应用领域
美国国家半导体 - NSC		控制器
页数	文件大小	规格书
58页	689K
描述
FuturebusaΛ Arbitration Controller

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DS3875 数据手册

November 1995

DS3875 Futurebus Arbitration Controller

General Description

The DS3875 Futurebus Arbitration Controller is a member

of National Semiconductor’s Futurebus chip set designed

User programmable 16 arbitration delays (8 slow and

8 fast)

specifically for the IEEE 896.1 Futurebus standard. The

Built-in PLL for accurate delays. The PLL accepts

clocks from 2 MHz to 40 MHz in steps of 1 MHz

Signal to unlock slave modules on transfer of tenure.

Auto unlock through a dummy cycle if the current mas-

ter locked resources

DS3875 implements Distributed Arbitration and Distributed

Arbitration messages in a single chip.

The DS3875 interfaces with Futurebus

through the

DS3885 BTL Arbitration Transceiver and the DS3884A BTL

Handshake Transceiver. The DS3885 BTL Arbitration

Transceiver incorporates the competition logic needed for

the Arbitration Number signal lines. The DS3884A BTL

Handshake Transceiver has selectable Wired-OR receiver

glitch filtering. The DS3884A is used for the Arbitration Se-

quencing and Arbitration Condition signal lines.

Programmable delay for releasing ar* after issuing

COMPETE/IBA CMPT. This is to ensure the assertion

of the arbitration number during competition, before the

release of ar*. Also this delay ensures there is suffi-

cient time to assert the AD/DATA lines during Idle Bus

Arbitration before the release of ar*

Read/Write facility with data acknowledge for the host

to load arbitration numbers, an arbitration message,

and control registers

Additional transceivers included in the Futurebus chip set

are the DS3883A BTL 9-bit Data Transceiver and the

DS3886A BTL 9-bit Latching Data Transceiver. The

DS3886A transceiver features edge-triggered latches in the

driver which may be bypassed during a fall-through mode

and a transparent latch in the receiver. The DS3883A trans-

ceiver has no latches in either direction.

On chip parity generator unloads the host of the addi-

tional parity generation function

Separate interrupts to indicate error occurrence and ar-

bitration message received. Interrupts cleared on a reg-

ister write. Error status is available in a separate status

The Logical Interface Futurebus Engine (LIFE) I/O Proto-

col Controller with 64-bit Data Path incorporates the Com-

Controller handles all the handshaking signals between the

Futurebus and the local bus interfaces, and incorporates

a DMA Controller with built-in FIFOs for fast queueing.

pelled Mode Futurebus

Parallel Protocol. The Protocol

special output pin to indicate that

message was received

a POWERFAIL

Hardwired register to hold the first word of the arbitra-

tion message

FIFO strobe provided to store more than one arbitration

message externally to prevent overrun

Idle Bus Arbitration (IBA) supported

Features

The controller implements the complete requirements

of the IEEE 896.1 specification as a subset of its fea-

tures

Parking implemented

Bus initialization, system reset and Live-insertion sup-

ported. (The logic to detect these conditions must be

implemented externally.)

Supports Arbitration message sending and receiving

Supports the two modes of operation (RESTRICTED/

UNRESTRICTED)

Testability in the form of reading from key registers

which include the STATE, MCW, 1 ms timer and pro-

grammable input clock divider

Software configurable double/single pass operation,

slow/fast, IBA/Parking and restricted/unrestricted

modes of arbitration

Built-in 1 ms timer for use in the arbitration cycle

TL/H/10747–1

National’s Futurebus Chip Set Diagram

1995 National Semiconductor Corporation

TL/H/10747

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7...58

中文翻译

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与DS3875相关器件

型号	品牌	获取价格	描述	数据表
DS3875V	NSC	获取价格	FuturebusaΛ Arbitration Controller
DS3875W/883	TI	获取价格	40MHz, BUS ARBITER AND CONT SIG GEN, CQFP68, CQD-68
DS3875W/883	NSC	获取价格	IC 40 MHz, BUS ARBITER AND CONT SIG GEN, CQFP68, CQD-68, System Interface Logic
DS3881	MAXIM	获取价格	Single-Channel Automotive CCFL Controller
DS3881E	MAXIM	获取价格	Single-Channel Automotive CCFL Controller
DS3881E/TR	MAXIM	获取价格	Switching Regulator/Controller, PDSO24,
DS3881E+	ROCHESTER	获取价格	FLUORESCENT LIGHT CONTROLLER, 100 kHz SWITCHING FREQ-MAX, PDSO24, 0.173 INCH, LEAD FREE, T
DS3881E+	MAXIM	获取价格	Fluorescent Light Controller, 100kHz Switching Freq-Max, PDSO24, 0.173 INCH, LEAD FREE, TS
DS3881E+C	MAXIM	获取价格	Fluorescent Light Controller, 100kHz Switching Freq-Max, PDSO24, 0.173 INCH, LEAD FREE, TS
DS3881E+T&R	MAXIM	获取价格	Fluorescent Light Controller, 100kHz Switching Freq-Max, PDSO24, 0.173 INCH, LEAD FREE, TS

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