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DS3647A

更新时间： 2024-01-27 02:28:23
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 152K
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DS3647A 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONALJESD-30 代码：R-PDIP-T16
JESD-609代码：e0逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：4功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified子类别：Bus Driver/Transceivers
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

DS3647A 数据手册

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February 1986  
DS3647A Quad TRI-STATE MOS Memory I/O Register  
É
General Description  
The DS3647A is a 4-bit I/O buffer register intended for use  
in MOS memory systems. This circuit employs a fall-through  
latch for data storage. This method of latching captures the  
data in parallel with the output, thus eliminating the delays  
encountered in other designs. This circuit uses Schottky-  
clamped transistor logic for minimum propagation delay and  
employs PNP input transistors so that input currents are  
low, allowing a large fan-out for this circuit which is needed  
in a memory system.  
The DS3647A features TRI-STATE outputs. The ‘‘B’’ port  
outputs are designed for use in bus organized data trans-  
b
mission systems and can sink 80 mA and source 5.2 mA.  
Data going from port ‘‘A’’ to port ‘‘B’’ and from ‘‘B’’ to port  
‘‘A’’ is inverted in the DS3647A.  
Features  
Y
PNP inputs minimize loading  
Y
Fall-through latch design  
Two pins per bit are provided, and data transfer is bi-direc-  
tional so that the register can handle both input and output  
data. The direction of data flow is controlled through the  
input enables. The latch control, when taken low, will cause  
the register to hold the data present at that time and display  
it at the outputs. Data can be latched into the register inde-  
pendent of the output disables or EXPANSION input. Either  
or both of the outputs may be taken to the high-impedance  
state with the output disables. The EXPANSION pin dis-  
ables both outputs to facilitate multiplexing with other I/O  
registers on the same data lines.  
Y
Propagation delay of only 15 ns  
Y
TRI-STATE outputs  
Y
EXPANSION control  
Y
Bi-directional data flow  
Y
TTL compatible  
Y
Transmission line driver output  
Logic and Connection Diagrams  
Dual-In-Line Package  
TL/F/8354–2  
Top View  
Order Number DS3647AD or DS3647AN  
See NS Package Number D16C or N16A  
TL/F/8354–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/F/8354  
RRD-B30M105/Printed in U. S. A.  
12345678

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与DS3647A相关器件

型号 品牌 获取价格 描述 数据表
DS3647AD ETC

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 		4-Bit Bus Transceiver
DS3647AD/A+ ETC

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 		4-Bit Bus Transceiver
DS3647AN ETC

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 		4-Bit Bus Transceiver
DS3647AN/A+ ETC

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 		4-Bit Bus Transceiver
DS3647AN/B+ ETC

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 		4-Bit Bus Transceiver
DS3647D ETC

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 		4-Bit Bus Transceiver
DS3647N ETC

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 		4-Bit Bus Transceiver
DS3647N/A+ ETC

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 		4-Bit Bus Transceiver
DS3647N/B+ ETC

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 		4-Bit Bus Transceiver
DS3648 NSC

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 		TRI-STATE TTL to MOS Multiplexers/Drivers

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