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DS34RT5110SQE

更新时间： 2024-11-23 06:54:39
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
20页 1883K
描述
DVI, HDMI Retimer with Input Equalization and Output De-Emphasis

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中文翻译

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DS34RT5110SQE 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：HVQCCN, LCC48,.27SQ,20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.02
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-XQCC-N48
长度：7 mm湿度敏感等级：1
功能数量：1端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Other Consumer ICs
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
表面贴装：YES温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

DS34RT5110SQE 数据手册

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PRELIMINARY  
May 11, 2009  
DS34RT5110  
DVI, HDMI Retimer with Input Equalization and Output De-  
Emphasis  
General Description  
Features  
The DS34RT5110 is a 10.2 Gbps (3 x 3.4 Gbps) high perfor-  
mance re-clocking device that supports 3 Transition Mini-  
mized Differential Signaling (TMDS®) data channels and a  
single clock channel over DVI™ v1.0, and HDMI™ v1.3a data  
rates up to 3.4 Gbps for each data channel. The device in-  
corporates a configurable receive equalizer, a clock and data  
recovery (CDR) circuit and a de-emphasis driver on each data  
channel. The clock channel feeds a high-performance phase-  
locked loop (PLL) that regenerates a low jitter output clock for  
data recovery.  
Optimized for HDMI/DVI repeater applications  
■
■
TMDS compatible inputs with configurable receive  
equalization supporting data rates up to 3.4 Gbps  
TMDS compatible outputs with configurable transmit de-  
emphasis  
■
Dedicated CDR on each data channel reduces jitter  
transfer, enabling multiple devices to be cascaded without  
impairing signal fidelity  
■
Capable of multi-hop extension of HDMI/DVI applications  
at data rates between 250 Mbps and 3.4 Gbps  
■
The DS34RT5110 equalizes and retimes greater than 25 me-  
ters 28 AWG of HDMI cable for 1080p resolution with 12 bit  
deep color depth (2.25 Gbps), to a low jitter version of the  
clock and data signal outputs, reducing both deterministic and  
random jitter. Several devices can be cascaded for long links  
without degrading signal fidelity. Obtaining total jitter is 0.09  
UI or less over the supported data rates. This low level of out-  
put jitter provides system designers with extra margin and  
flexibility when working with stringent timing budgets.  
Resistor adjustable differential output voltage for AC  
coupled Cat5e and Cat6 extension applications  
2 equalizer settings for a wide range of cable reaches at  
different data rates  
■
■
Total Output Jitter of 0.09 UI at 2.25 Gbps  
■
■
■
Total Output Jitter of 0.10 UI at 3.4 Gbps  
DVI 1.0 and HDMI v1.3a compatible TMDS source and  
sink interface  
The transmitter supports configurable transmit de-emphasis  
so the output can be optimized for driving additional lengths  
of cables or FR4 traces.  
7 mm x 7 mm 48 pin LLP package  
■
■
■
>8 kV HBM ESD protection  
0 °C to +70 °C operating temperature  
Applications  
Repeater Applications  
■
Digital Routers  
—
—
HDMI / DVI Extender Multi-hops  
Source Applications  
■
■
Video Cards  
—
—
—
Blu-ray DVD Players  
Game Consoles  
Sink Applications  
High Definition Displays  
Projectors  
—
—
Application Diagram  
30087353  
© 2009 National Semiconductor Corporation  
300873  
www.national.com  
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