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DS32EL0124SQX

更新时间： 2024-01-26 19:46:25

品牌	Logo	应用领域
美国国家半导体 - NSC		驱动器接口集成电路双倍数据速率
页数	文件大小	规格书
28页	1547K
描述
125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

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DS32EL0124SQX 数据手册

November 9, 2009

DS32EL0124, DS32ELX0124

125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR

LVDS Parallel Interface

General Description

Features

The DS32EL0124/DS32ELX0124 integrates clock and data

recovery modules for high-speed serial communication over

FR-4 printed circuit board backplanes, balanced cables, and

optical fiber. This easy-to-use chipset integrates advanced

signal and clock conditioning functions, with an FPGA friendly

interface.

5-bit DDR LVDS parallel data interface

■

Programmable Receive Equalization

Selectable DC-balance decoder

Selectable De-scrambler

Remote Sense for automatic detection and negotiation of

link status

■

The DS32EL0124/DS32ELX0124 deserializes up to 3.125

Gbps of high speed serial data to 5 LVDS outputs without the

need for an external reference clock. With DC-balance de-

coding enabled, the application payload of 2.5 Gbps is dese-

rialized to 4 LVDS outputs.

No external receiver reference clock required

■

LVDS parallel interface

Programmable LVDS output clock delay

Supports output data-valid signaling

The DS32EL0124/DS32ELX01214 deserializers feature a re-

mote sense capability to automatically signal link status con-

ditions to its companion DS32EL0421/ELX0421 serializers

without requiring an additional feedback path.

Supports keep-alive clock output

On chip LC VCOs

Redundant serial input (ELX device only)

The parallel LVDS interface of these devices reduce FPGA

I/O pins, board trace count and alleviates EMI issues, when

compared to traditional single-ended wide bus interfaces.

Retimed serial output (ELX device only)

Configurable PLL loop bandwidth

Configurable via SMBus

The DS32EL0124/ELX0124 is programmable through a SM-

Bus interface as well as through control pins.

Loss of lock and error reporting

48-pin LLP package with exposed DAP

Applications

Key Specifications

Imaging: Industrial, Medical Security, Printers

■

1.25 to 3.125 Gbps serial data rate

■

Displays: LED walls, Commercial

125 to 312.5 MHz DDR parallel clock

Video Transport

-40° to +85°C temperature range

Communication Systems

> 8 kV ESD (HBM) protection

Test and Measurement

■

0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

■

Industrial Bus

■

Typical Application

30043101

300431

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与DS32EL0124SQX相关器件

型号	品牌	获取价格	描述	数据表
DS32EL0124SQX/NOPB	TI	获取价格	具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link
DS32EL0421	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421	NSC	获取价格	125 - 312.5 MHz Serializer with DDR LVDS Parallel LVDS Interface
DS32EL0421_0807	NSC	获取价格	125 - 312.5 MHz Serializer with DDR LVDS Parallel LVDS Interface
DS32EL0421_09	NSC	获取价格	125-312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface
DS32EL0421SQ	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421SQ/NOPB	TI	获取价格	具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link
DS32EL0421SQE	TI	获取价格	5-bit DDR LVDS Parallel Data Interface
DS32EL0421SQE/NOPB	TI	获取价格	125 MHz - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface 48-WQFN -40 to 8
DS32EL0421SQX	TI	获取价格	5-bit DDR LVDS Parallel Data Interface

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