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DS32EL0124SQ PDF预览

DS32EL0124SQ

更新时间: 2024-09-27 06:54:39
品牌 Logo 应用领域
美国国家半导体 - NSC 线路驱动器或接收器驱动程序和接口接口集成电路双倍数据速率
页数 文件大小 规格书
28页 1547K
描述
125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface

DS32EL0124SQ 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:LLP-48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
差分输出:YES驱动器位数:2
接口集成电路类型:LINE TRANSCEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:S-XQCC-N48JESD-609代码:e0
长度:7 mm湿度敏感等级:2
功能数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源:2.5,3.3 V
认证状态:Not Qualified最大接收延迟:
接收器位数:2座面最大高度:0.8 mm
子类别:Line Driver or Receivers最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
电源电压1-最大:3.465 V电源电压1-分钟:3.135 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:7 mm
Base Number Matches:1

DS32EL0124SQ 数据手册

 浏览型号DS32EL0124SQ的Datasheet PDF文件第2页浏览型号DS32EL0124SQ的Datasheet PDF文件第3页浏览型号DS32EL0124SQ的Datasheet PDF文件第4页浏览型号DS32EL0124SQ的Datasheet PDF文件第5页浏览型号DS32EL0124SQ的Datasheet PDF文件第6页浏览型号DS32EL0124SQ的Datasheet PDF文件第7页 
November 9, 2009  
DS32EL0124, DS32ELX0124  
125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR  
LVDS Parallel Interface  
General Description  
Features  
The DS32EL0124/DS32ELX0124 integrates clock and data  
recovery modules for high-speed serial communication over  
FR-4 printed circuit board backplanes, balanced cables, and  
optical fiber. This easy-to-use chipset integrates advanced  
signal and clock conditioning functions, with an FPGA friendly  
interface.  
5-bit DDR LVDS parallel data interface  
Programmable Receive Equalization  
Selectable DC-balance decoder  
Selectable De-scrambler  
Remote Sense for automatic detection and negotiation of  
link status  
The DS32EL0124/DS32ELX0124 deserializes up to 3.125  
Gbps of high speed serial data to 5 LVDS outputs without the  
need for an external reference clock. With DC-balance de-  
coding enabled, the application payload of 2.5 Gbps is dese-  
rialized to 4 LVDS outputs.  
No external receiver reference clock required  
LVDS parallel interface  
Programmable LVDS output clock delay  
Supports output data-valid signaling  
The DS32EL0124/DS32ELX01214 deserializers feature a re-  
mote sense capability to automatically signal link status con-  
ditions to its companion DS32EL0421/ELX0421 serializers  
without requiring an additional feedback path.  
Supports keep-alive clock output  
On chip LC VCOs  
Redundant serial input (ELX device only)  
The parallel LVDS interface of these devices reduce FPGA  
I/O pins, board trace count and alleviates EMI issues, when  
compared to traditional single-ended wide bus interfaces.  
Retimed serial output (ELX device only)  
Configurable PLL loop bandwidth  
Configurable via SMBus  
The DS32EL0124/ELX0124 is programmable through a SM-  
Bus interface as well as through control pins.  
Loss of lock and error reporting  
48-pin LLP package with exposed DAP  
Applications  
Key Specifications  
Imaging: Industrial, Medical Security, Printers  
1.25 to 3.125 Gbps serial data rate  
Displays: LED walls, Commercial  
125 to 312.5 MHz DDR parallel clock  
Video Transport  
-40° to +85°C temperature range  
Communication Systems  
> 8 kV ESD (HBM) protection  
Test and Measurement  
0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)  
Industrial Bus  
Typical Application  
30043101  
© 2009 National Semiconductor Corporation  
300431  
www.national.com  

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