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DS26LS33C

更新时间： 2024-01-29 18:02:28
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
6页 143K
描述
Quad Differential Line Receivers

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DS26LS33C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DFP, FL16,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-XDFP-F16
JESD-609代码：e0端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
最大输出低电流：0.008 A封装主体材料：CERAMIC
封装代码：DFP封装等效代码：FL16,.3
封装形状：RECTANGULAR封装形式：FLATPACK
电源：5 V认证状态：Not Qualified
最大接收延迟：25 ns筛选级别：MIL-STD-883 Class B (Modified)
子类别：Line Driver or Receivers标称供电电压：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

DS26LS33C 数据手册

 浏览型号DS26LS33C的Datasheet PDF文件第2页浏览型号DS26LS33C的Datasheet PDF文件第3页浏览型号DS26LS33C的Datasheet PDF文件第4页浏览型号DS26LS33C的Datasheet PDF文件第5页浏览型号DS26LS33C的Datasheet PDF文件第6页 
January 1996  
DS26LS32C/DS26LS32M/DS26LS32AC/DS26LS33C/  
DS26LS33M/DS26LS33AC Quad Differential Line  
Receivers  
General Description  
Features  
Y
High differential or common-mode input voltage ranges  
The DS26LS32 and DS26LS32A are quad differential line  
receivers designed to meet the RS-422, RS-423 and Feder-  
al Standards 1020 and 1030 for balanced and unbalanced  
digital data transmission.  
g
g
of 7V on the DS26LS32 and DS26LS32A and 15V  
on the DS26LS33 and DS26LS33A  
Y
Y
g
0.2V sensitivity over the input voltage range on the  
g
DS26LS32 and DS26LS32A,  
DS26LS33 and DS26LS33A  
0.5V sensitivity on the  
The DS26LS32 and DS26LS32A have an input sensitivity of  
g
DS26LS33 and DS26LS33A have an input sensitivity of  
200 mV over the input voltage range of  
7V and the  
DS26LS32 and DS26LS32A meet all requirements of  
RS-422 and RS-423  
g
500 mV over the input voltage range of 15V.  
Y
Y
6k minimum input impedance  
Both the DS26LS32A and DS26LS33A differ in function  
from the popular DS26LS32 and DS26LS33 in that input  
pull-up and pull-down resistors are included which prevent  
output oscillation on unused channels.  
100 mV input hysteresis on the DS26LS32 and  
DS26LS32A, 200 mV on the DS26LS33 and  
DS26LS33A  
Y
Y
Operation from a single 5V supply  
Each version provides an enable and disable function com-  
mon to all four receivers and features TRI-STATE outputs  
with 8 mA sink capability. Constructed using low power  
Schottky processing, these devices are available over the  
full military and commerical operating temperature ranges.  
TRI-STATE outputs, with choice of complementary out-  
put enables for receiving directly onto a data bus  
É
Logic Diagram  
TL/F/5255–1  
Connection Diagram  
Truth Table  
ENABLE  
ENABLE  
Input  
Output  
Dual-In-Line Package  
0
1
X
Hi-Z  
1
t
See  
V
V
V
V
(Max)  
(Min)  
ID  
TH  
Note Below  
s
0
ID  
TH  
e
HI-Z  
TRI-STATE  
Note: Input conditions may be any combination not defined for ENABLE  
and ENABLE.  
Order Number DS26LS32CM, DS26LS32CN,  
DS26LS32MJ, DS26LS32ACM, DS26LS32ACN,  
DS26LS33CN, DS26LS33MJ or DS26LS33ACN  
See NS Package Number J16A, M16A or N16A  
For Complete Military 883 Specifications,  
See RETS Data Sheet.  
TL/F/5255–2  
Top View  
Order Number DS26LS32MJ/883, DS26LS32MW/883,  
DS26LS33MJ/883, DS26LS33MW/883  
See NS Package Number J16A or W16A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1996 National Semiconductor Corporation  
TL/F/5255  
RRD-B30M36/Printed in U. S. A.  
http://www.national.com  
123456

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