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DS26LS32 PDF预览

DS26LS32

更新时间: 2024-11-23 22:50:51
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美国国家半导体 - NSC /
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8页 205K
描述
Quad Differential Line Receivers

DS26LS32 数据手册

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May 1999  
DS26LS32AC/DS26LS32C/DS26LS32M/DS26LS33M  
Quad Differential Line Receivers  
General Description  
Features  
n High differential or common-mode input voltage ranges  
The DS26LS32 and DS26LS32A are quad differential line re-  
ceivers designed to meet the RS-422, RS-423 and Federal  
Standards 1020 and 1030 for balanced and unbalanced digi-  
tal data transmission.  
±
±
of 7V on the DS26LS32 and DS26LS32A and 15V  
on the DS26LS33  
±
n
0.2V sensitivity over the input voltage range on the  
±
DS26LS32 and DS26LS32A, 0.5V sensitivity on the  
DS26LS33  
The DS26LS32 and DS26LS32A have an input sensitivity of  
±
200 mV over the input voltage range of 7V and the  
n DS26LS32 and DS26LS32A meet all requirements of  
RS-422 and RS-423  
DS26LS33 have an input sensitivity of 500 mV over the input  
±
voltage range of 15V.  
n 6k minimum input impedance  
The DS26LS32A differ in function from the popular  
DS26LS32 and DS26LS33 in that input pull-up and  
pull-down resistors are included which prevent output oscil-  
lation on unused channels.  
n 100 mV input hysteresis on the DS26LS32 and  
DS26LS32A, 200 mV on the DS26LS33  
n Operation from a single 5V supply  
n TRI-STATE outputs, with choice of complementary  
output enables for receiving directly onto a data bus  
Each version provides an enable and disable function com-  
mon to all four receivers and features TRI-STATE outputs  
®
with 8 mA sink capability. Constructed using low power  
Schottky processing, these devices are available over the  
full military and commerical operating temperature ranges.  
Logic Diagram  
DS005255-1  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS005255  
www.national.com  

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