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DS2188S/T&R PDF预览

DS2188S/T&R

更新时间: 2024-10-28 14:41:51
品牌 Logo 应用领域
美信 - MAXIM 衰减器PC电信光电二极管电信集成电路
页数 文件大小 规格书
10页 135K
描述
PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16

DS2188S/T&R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.33.00.01Factory Lead Time:1 week
风险等级:5.65运营商类型:CEPT PCM-30/E-1
运营商类型(2):T-1(DS1)JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.335 mm
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):245电源:5 V
认证状态:Not Qualified座面最大高度:2.68 mm
子类别:Other Telecom ICs最大压摆率:0.012 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:PCM JITTER ATTENUATOR
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.51 mmBase Number Matches:1

DS2188S/T&R 数据手册

 浏览型号DS2188S/T&R的Datasheet PDF文件第2页浏览型号DS2188S/T&R的Datasheet PDF文件第3页浏览型号DS2188S/T&R的Datasheet PDF文件第4页浏览型号DS2188S/T&R的Datasheet PDF文件第5页浏览型号DS2188S/T&R的Datasheet PDF文件第6页浏览型号DS2188S/T&R的Datasheet PDF文件第7页 
DS2188  
T1/CEPT Jitter Attenuator  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
Attenuates clock and data jitter present in T1  
or CEPT lines  
DJA  
RPOS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VDD  
RRPOS  
RRNEG  
RRCLK  
RST  
Meets the jitter attenuation templates  
outlined in TR62411, TR-TSY-000170,  
G.735, and G.742  
Only one external component required; either  
a 6.176 MHz (T1) or 8.192 MHz (CEPT)  
crystal  
Selectable buffer size of 128 or 32 bits  
Jitter attenuation is easily disabled  
Single +5V supply; low-power CMOS  
technology  
Available in 16-pin DIP and 16-pin SOIC  
(DS2188S)  
RNEG  
RCLK  
BDS  
TEST  
BL  
XTAL OUT  
VSS  
XTAL2  
XTAL1  
ORDERING INFORMATION  
DS2188  
DS2188S  
DS2188N  
16 Pin dip  
16 Pin SOIC (0º-+70ºC)  
16 Pin dip (-40ºC-+85ºC)  
(0ºC-F70ºC)  
Companion to the DS2186 Transmit Line  
and DS2187 Receive Line Interface  
DS2188SN 16 Pin SOIC (-40ºC-+85-ºC)  
DESCRIPTION  
The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an  
external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all  
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service  
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect  
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and  
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A  
CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186  
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network  
Interface Unit.  
OVERVIEW  
The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and  
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency  
of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a  
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than  
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and  
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer  
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.  
If the incoming jitter has excursions greater than 120 UIpp, then the crystal is adjusted to track the short-  
term frequency variations of the incoming signal so that there is no loss of data. This adjustment is  
accomplished by dividing the 4X crystal by either 3 ½ or 4 ½ instead of 4. When the incoming jitter is  
1 of 10  
100600  

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