DS2188

更新时间： 2024-10-27 22:50:51

品牌	Logo	应用领域
达拉斯 - DALLAS		衰减器
页数	文件大小	规格书
11页	152K
描述
T1/CEPT Jitter Attenuator

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技术参数
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DS2188 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	DIP-16	Reach Compliance Code：	unknown
风险等级：	5.62	运营商类型：	CEPT PCM-30/E-1
运营商类型（2）：	T-1(DS1)	JESD-30 代码：	R-PDIP-T16
JESD-609代码：	e0	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	5 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	最大压摆率：	12 mA
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	电信集成电路类型：	PCM JITTER ATTENUATOR
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

DS2188 数据手册

DS2188

T1/CEPT Jitter Attenuator

www.dalsemi.com

FEATURES

§ Attenuates clock and data jitter present in T1

or CEPT lines

PIN ASSIGNMENT

§ Meets the jitter attenuation templates

outlined in TR62411, TR-TSY-000170,

G.735, and G.742

§ Only one external component required; either

a 6.176 MHz (T1) or 8.192 MHz (CEPT)

crystal

§ Selectable buffer size of 128 or 32 bits

§ Jitter attenuation is easily disabled

§ Single +5V supply; low-power CMOS

technology

DJA

RPOS

VDD

RRPOS

RRNEG

RRCLK

RST

RNEG

RCLK

BDS

TEST

XTAL OUT

VSS

XTAL2

XTAL1

§ Available in 16-pin DIP and 16-pin SOIC

(DS2188S)

16-Pin DIP/SOIC

§ Companion to the DS2186 Transmit Line

and DS2187 Receive Line Interface

DESCRIPTION

The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an

external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all

of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service

Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect

System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and

G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A

CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186

T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network

Interface Unit.

OVERVIEW

The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and

negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency

of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a

DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than

120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and

it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer

Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.

1 of 11

092299

12 3 4 5 6 7...11

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与DS2188相关器件

型号	品牌	获取价格	描述	数据表
DS2188+	MAXIM	获取价格	PCM Jitter Attenuator, 1-Func, CMOS, PDIP16, DIP-16
DS2188N	ETC	获取价格	PCM Transceiver
DS2188S	MAXIM	获取价格	PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16
DS2188S/T&R	MAXIM	获取价格	PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16
DS2188SN	ETC	获取价格	PCM Transceiver
DS2188SN/T&R	MAXIM	获取价格	PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16
DS2188SN+	MAXIM	获取价格	PCM Jitter Attenuator, 1-Func, CEPT PCM-30/E-1, CMOS, PDSO16, SOIC-16
DS2189	MAXIM	获取价格	PCM Receiver, CEPT PCM-30/E-1, Bipolar, PDIP24,
DS2189S	MAXIM	获取价格	PCM Receiver, CEPT PCM-30/E-1, Bipolar, PDSO24,
DS219	ETC	获取价格	Analog IC

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