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DS2152LN

更新时间： 2024-10-28 22:34:39
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
94页 1000K
描述
Enhanced T1 Single-Chip Transceiver

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中文翻译

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DS2152LN 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：LQFP-100Reach Compliance Code：unknown
风险等级：5.71运营商类型：T-1(DS1)
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
功能数量：1端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK电源：5 V
认证状态：Not Qualified子类别：Other Telecom ICs
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：FRAMER
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUADBase Number Matches：1

DS2152LN 数据手册

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DS2152  
Enhanced T1 Single-Chip Transceiver  
www.dalsemi.com  
FEATURES  
PIN ASSIGNMENT  
§
Complete DS1/ISDN-PRI transceiver  
functionality  
§
Line interface can handle both long and short haul  
trunks  
§
§
§
§
32-bit or 128-bit crystal-less jitter attenuator  
Generates DSX-1 and CSU line build outs  
Frames to D4, ESF, and SLC-96R formats  
Dual onboard two-frame elastic store slip buffers  
that can connect to asynchronous backplanes up to  
8.192 MHz  
§
8-bit parallel control port that can be used directly  
on either multiplexed or non-multiplexed buses  
(Intel or Motorola)  
§
§
Extracts and inserts robbed-bit signaling  
Detects and generates yellow (RAI) and blue  
(AIS) alarms  
§
§
Programmable output clocks for Fractional T1  
Fully independent transmit and receive  
functionality  
1
ORDERING INFORMATION  
§
§
Integral HDLC controller with 16-byte buffers for  
the FDL  
DS2152L  
(0°C to 70°C)  
(-40°C to +85°C)  
Generates and detects in-band loop codes from 1  
to 8 bits in length including CSU loop codes  
Contains ANSI 1's density monitor and enforcer  
Large path and line error counters including BPV,  
CV, CRC6, and framing bit errors  
Pin compatible with DS2154 E1 Enhanced Single-  
Chip Transceiver  
DS2152LN  
§
§
§
§
§
5V supply; low power CMOS  
100-pin 14mm2 body LQFP package  
DESCRIPTION  
The DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection  
to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry  
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both  
DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter  
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data  
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It  
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set  
of internal registers which the user can access and control the operation of the unit. Quick access via the  
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the  
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),  
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.  
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中文翻译

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DS2153Q DALLAS

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DS2153Q+ MAXIM

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DS2153Q-A7/TR+ MAXIM

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DS2153Q-A7+T&R MAXIM

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 		Framer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44
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 		PCM Transceiver
DS2153QN+ MAXIM

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 		Framer, CMOS, PQCC44, 0.652 INCH, ROHS COMPLIANT, PLASTIC, LCC-44
DS2153QN-A7/T&R MAXIM

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 		Framer, CMOS, PQCC44, 0.652 INCH, PLASTIC, LCC-44
DS2153QN-A7/TR+ MAXIM

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 		Telecom IC, CMOS, PQCC44

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