DS21372TN

更新时间： 2024-11-24 22:50:47

品牌	Logo	应用领域
达拉斯 - DALLAS		电信集成电路电信电路测试
页数	文件大小	规格书
21页	216K
描述
3.3V Bit Error Rate Tester BERT

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中文翻译

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技术参数
数据手册

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DS21372TN 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TQFP-32	Reach Compliance Code：	unknown
风险等级：	5.7	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G32	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	FLATPACK
认证状态：	Not Qualified	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子位置：	QUAD	Base Number Matches：	1

DS21372TN 数据手册

DS21372

3.3V Bit Error Rate Tester (BERT)

www.dalsemi.com

PIN ASSIGNMENT

FEATURES

ꢀ Generates/detects digital bit patterns for

analyzing, evaluating and troubleshooting

digital communications systems

ꢀ Operates at speeds from DC to 20 MHz

ꢀ Programmable polynomial length and

feedback taps for generation of any other

pseudorandom pattern up to 32 bits in length

including: 2⁶-1, 2⁹-1, 2¹¹-1, 2¹⁵-1, 2²⁰-1, 2²³-1,

and 2³²-1

32 31 30 29 28 27 26 25

AD0

AD1

TEST

VSS

AD2

AD3

AD4

RLOS

VSS

VDD

INT

WR(R/W)

ALE(AS)

DS21372

32-PIN TQFP

ꢀ Programmable user-defined pattern and

length for generation of any repetitive pattern

up to 32 bits in length

9 10 11 12 13 14 15 16

ꢀ Large 32-bit error count and bit count

registers

ꢀ Software programmable bit error insertion

ꢀ Fully independent transmit and receive

sections

ORDERING INFORMATION

ꢀ 8-bit parallel control port

DS21372T

(0⁰C to 70⁰C)

ꢀ Detects test patterns with bit error rates up to

DS21372TN

(-40⁰C to +85⁰C)

10^-2

DESCRIPTION

The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,

and analyzer capable of meeting the most stringent error performance requirements of digital

transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)

conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates

ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in

existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,

Routers, Bridges, CSUs, DSUs, and CPE equipment.

The DS21372 user-programmable pattern registers provide the unique ability to generate loopback

patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can

initiate the loopback, run the test, check for errors, and finally deactivate the loopback.

The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and

control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up

to 2³²-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic

inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-

T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the

DS21372 can insert single or 10^-1to 10^-7bit errors to verify equipment operation and connectivity.

1 of 21

050400

12 3 4 5 6 7...21

中文翻译

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与DS21372TN相关器件

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DS2141AQ+	MAXIM	获取价格	Framer, CMOS, PQCC44, PLASTIC, LCC-44

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