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DS21352L

更新时间： 2024-11-24 22:50:47
品牌 Logo 应用领域
达拉斯 - DALLAS 电信集成电路PC
页数 文件大小 规格书
137页 1017K
描述
3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

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中文翻译

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DS21352L 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：14 X 14 MM, LQFP-100Reach Compliance Code：unknown
风险等级：5.59运营商类型：T-1(DS1)
JESD-30 代码：S-PQFP-G100JESD-609代码：e0
功能数量：1端子数量：100
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK电源：3.3 V
认证状态：Not Qualified子类别：Other Telecom ICs
标称供电电压：3.3 V表面贴装：YES
技术：CMOS电信集成电路类型：PCM TRANSCEIVER
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUADBase Number Matches：1

DS21352L 数据手册

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3.3V DS21352 and 5V DS21552  
T1 Single-Chip Transceivers  
www.maxim-ic.com  
FEATURES  
PIN ASSIGNMENT  
C
C
C
C
C
Complete DS1/ISDN–PRI/J1 transceiver functionality  
Long and Short haul LIU  
Crystal–less jitter attenuator  
Generates DSX–1 and CSU line build-outs  
HDLC controller with 64-byte buffers Configurable for  
FDL or DS0 operation  
C
Dual two–frame elastic store slip buffers that can  
connect to asynchronous backplanes up to 8.192MHz  
8.192MHz clock output locked to RCLK  
Interleaving PCM Bus Operation  
DS21352  
DS21552  
C
C
C
C
Per-channel loopback and idle code insertion  
8-bit parallel control port muxed or nonmuxed buses  
(Intel or Motorola)  
100  
C
C
C
Programmable output clocks for Fractional T1  
Fully independent transmit and receive functionality  
Generates/detects in-band loop codes from 1 to 8 bits  
in length including CSU loop codes  
1
C
C
C
IEEE 1149.1 JTAG-Boundary Scan  
Pin compatible with DS2152/54/354/554 SCTs  
100-pin LQFP package (14 mm x 14 mm) 3.3V  
(DS21352) or 5V (DS21552) supply; low power  
CMOS  
ORDERING INFORMATION  
DS21352L  
DS21352LN  
DS21552L  
DS21552LN  
(0LC to +70LC)  
(-40LC to +85LC)  
(0LC to +70LC)  
(-40LC to +85LC)  
DESCRIPTION  
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1  
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically  
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build  
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator  
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The  
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also  
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of  
internal registers which the user can access and control the operation of the unit. Quick access via the  
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the  
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),  
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.  
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