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DS1706S

更新时间： 2024-11-12 22:40:35
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
10页 78K
描述
3.3 and 5.0 Volt MicroMonitor

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中文翻译

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DS1706S 数据手册

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DSDS1705/DS1706  
DS1705/DS1706  
3.3 and 5.0 Volt MicroMonitor  
FEATURES  
PIN ASSIGNMENT  
• Halts and restarts an out–of–control microprocessor  
PBRST  
1
2
3
4
8
7
6
5
WDS  
RST  
ST  
• Holds microprocessor in check during power tran-  
sients  
V
CC  
GND  
IN  
NMI  
• Automatically restarts microprocessor after power  
failure  
8–PIN DIP  
(300 MIL)  
• Monitors pushbutton for external override  
PBRST  
1
2
3
4
8
7
6
5
WDS  
• Accurate 5%, 10% or 20% resets for 3.3 systems and  
5% or 10% resets for 5.0 volt systems  
V
RST (*RST)  
ST  
CC  
GND  
IN  
NMI  
• Eliminates the need for discrete components  
8–PIN SOIC  
(150 MIL)  
• 3.3 volt 20% tolerance for use with 3.0 volt systems  
• Pin compatible with the MAXIM MAX705/MAX706 in  
PBRST  
VCC  
GND  
IN  
1
2
3
4
8
7
6
5
WDS  
8–pin DIP and 8–pin SOIC  
RST (*RST)  
ST  
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages  
• Industrial temperature range –40°C to +85°C  
NMI  
8–PIN µ–SOP  
(118 MIL)  
See Mech. Drawings  
Section  
DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P)  
PIN DESCRIPTION  
PBRST  
–
–
–
–
–
–
–
–
Pushbutton Reset Input  
Power Supply  
Ground  
V
CC  
GND  
IN  
NMI  
ST  
RST  
*RST  
Input  
Non–maskable Interrupt  
Strobe Input  
Active Low Reset Output  
Active High Reset Output  
(DS1706P and DS1706L only)  
Watchdog Status Output  
WDS  
–
DESCRIPTION  
TheDS1705/DS17063.3or5.0VoltMicroMonitormoni-  
tors three vital conditions for a microprocessor: power  
supply, software execution, and external override. A  
precision temperature compensated reference and  
condition a non–maskable interrupt is generated. As  
the voltage at the device degrades an internal power fail  
signal is generated which forces the reset to an active  
state. When V returns to an in–tolerance condition,  
CC  
comparator circuit monitors the status of V  
device and at an upstream point for maximum protec-  
tion. When the sense input detects an out–of–tolerance  
at the  
the reset signal is kept in the active state for a minimum  
of 130 ms to allow the power supply and processor to  
stabilize.  
CC  
ECopyright 1995 by Dallas Semiconductor Corporation.  
All Rights Reserved. For important information regarding  
patents and other intellectual property rights, please refer to  
Dallas Semiconductor data books.  
011296 1/10  
1234567...10

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