Datasheet > DS1034

DS1034

更新时间： 2024-09-19 14:57:43

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莱迪思 - LATTICE		/
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ProcessorPM - POWR605 Data Sheet

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DS1034 数据手册

ProcessorPM-POWR605

In-System Programmable Power Supply Supervisor,

Reset Generator and Watchdog Timer

April 2015

Data Sheet DS1034

Features

Application Block Diagram

 Precision Programmable Threshold

Input Power Supply

Monitors, Threshold Accuracy 0.7%

• Simultaneously monitors up to six power supplies

• Programmable analog trip points (1% step size;

192 steps)

DC-DC

Manual

Reset In

• Programmable glitch filter

Power

Supply

Bus

• Power-off detection (75 mV)

 Embedded Programmable Timers

• Four independent timers

• 32 µs to 2 second intervals for timing sequences

Voltage Supervisor

Interrupt –

Power Fail

 Embedded PLD for Logical Control

• Rugged 16-macrocell CPLD architecture

• 81 product terms / 28 inputs

Reset Generator

Watchdog Timer

Power Down

CPU_Reset_in

• Implements state machines and combinatorial

functions

WDT Trigger

Interrupt – WDT

 Power-Down Mode I_CC< 10 µA

 Digital I/O

CPU /

uProcessor

• Two dedicated digital inputs

• Five programmable digital I/O pins

ProcessorPM-

POWR605

 Wide Supply Range (2.64 V to 3.96 V)

• In-system programmable through JTAG

• Industrial temperature range: –40 °C to +105 °C

• 24-pin QFN package, lead-free option

Power Up/Down Control

The diagram above shows how a ProcessorPM-

POWR605 is used in a typical application. It controls

power to the microprocessor system, generates the

CPU reset and monitors critical power supply voltages,

generating interrupts whenever faults are detected. It

also provides a watchdog timer function to detect CPU

operating and bus timeout errors.

Description

Lattice’s Power Manager II ProcessorPM-POWR605 is

a general-purpose power-supply monitor, reset genera-

tor and watchdog timer, incorporating both in-system

programmable logic and analog functions implemented

in non-volatile E²CMOS^®technology. The Proces-

sorPM-POWR605 device provides six independent ana-

log input channels to monitor power supply voltages.

Two general-purpose digital inputs are also provided for

miscellaneous control functions.

The ProcessorPM-POWR605 incorporates a 16-macro-

cell CPLD. Figure 1 shows the analog input compara-

tors and digital inputs used as inputs to the CPLD array.

The digital output pins providing the external control sig-

nals are driven by the CPLD. Four independently pro-

grammable timers also interface with the CPLD and can

create delays and time-outs ranging from 32 µs to 2

seconds. The CPLD is programmed using Logi-

Builder™, an easy-to-learn language integrated into the

PAC-Designer^®software. Control sequences are written

to monitor the status of any of the analog input channel

comparators or the digital inputs.

The ProcessorPM-POWR605 provides up to five open

drain digital outputs that can be used for controlling DC-

DC converters, low-drop-out regulators (LDOs) and opt-

ocouplers, as well as for supervisory and general-pur-

pose logic interface functions. The five digital, open

drain outputs can optionally be configured as digital

inputs to sense more input signals as needed, such as

manual reset, etc.

brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without

notice.

www.latticesemi.com

DS1034_2.0

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