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DP8419D-70 PDF预览

DP8419D-70

更新时间： 2024-11-18 22:09:23
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器内存控制器
页数 文件大小 规格书
28页 525K
描述
64k, 256k Dynamic RAM Controller/Drivers

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中文翻译

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DP8419D-70 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP48,.6Reach Compliance Code：unknown
风险等级：8.74地址总线宽度：18
边界扫描：NO最大时钟频率：70 MHz
外部数据总线宽度：JESD-30 代码：R-CDIP-T48
JESD-609代码：e0低功率模式：NO
内存组织：256K X 1区块数量：4
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP48,.6
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Memory Controllers最大压摆率：240 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：NO
技术：BIPOLAR温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15.24 mm
uPs/uCs/外围集成电路类型：MEMORY CONTROLLER, DRAM

DP8419D-70 数据手册

 浏览型号DP8419D-70的Datasheet PDF文件第2页浏览型号DP8419D-70的Datasheet PDF文件第3页浏览型号DP8419D-70的Datasheet PDF文件第4页浏览型号DP8419D-70的Datasheet PDF文件第5页浏览型号DP8419D-70的Datasheet PDF文件第6页浏览型号DP8419D-70的Datasheet PDF文件第7页 
PRELIMINARY  
August 1989  
DP8417/NS32817, 8418/32818, 8419/32819, 8419X/  
32819X 64k, 256k Dynamic RAM Controller/Drivers  
General Description  
Operational Features  
Y
Makes DRAM Interface and refresh tasks appear virtu-  
ally transparent to the CPU, making DRAMs as easy to  
use as static RAMs  
The DP8417/8418/8419/8419X represent a family of 256k  
DRAM Controller/Drivers which are designed to provide  
‘‘No-Waitstate’’ CPU interface to Dynamic RAM arrays of up  
to 2 Mbytes and larger. Each device offers slight functional  
variations of the DP8419 design which are tailored for differ-  
ent system requirements. All family members are fabricated  
using National’s new oxide isolated Advanced Low power  
Schottky (ALS) process and use design techniques which  
enable them to significantly out-perform all other LSI or dis-  
crete alternatives in speed, level of integration, and power  
consumption.  
Y
Specifically designed to eliminate CPU wait states up to  
10 MHz or beyond  
Y
Eliminates 15 to 20 SSI/MSI components for significant  
board real estate reduction, system power savings and  
the elimination of chip-to-chip AC skewing  
Y
On-board ultra precise delay line  
Y
On-board high capacitive RAS, CAS, WE, and address  
drivers (specified driving 88 DRAMs directly)  
Each device integrates the following critical 256k DRAM  
controller functions on a single monolithic device: ultra pre-  
cise delay line; 9-bit refresh counter; fall-through row, col-  
umn, and bank select input latches; Row/Column address  
muxing logic; on-board high capacitive-load RAS, CAS, and  
Write Enable & Address output drivers; and, precise control  
signal timing for all the above.  
Y
AC specified for directly addressing up to 8 Megabytes  
Y
Low power/high speed bipolar oxide isolated process  
Y
Upward pin and function compatible with new DP8428/  
DP8429 1 Mbit DRAM controller drivers  
Y
Downward pin and function compatible with DP8408A/  
DP8409A 64k/256k DRAM controller/drivers  
Y
4 user selectable modes of operation for Access and  
Refresh (2 automatic, 2 external)  
There are four device options of the basic DP8419 Control-  
ler. The DP8417 is pin and function compatible with the  
DP8419 except that its outputs are TRI-STATE  
. The  
É
Contents  
Y
DP8418 changes one pin and is specifically designed to  
offer an optimum interface to 32 bit microprocessors. The  
DP8419X is functionally identical to the DP8419, but is avail-  
able in a 52-pin DIP package which is upward pin compati-  
ble with National’s new DP8429D 1 Mbit DRAM Controller/  
Driver.  
System and Device Block Diagrams  
Y
Recommended Companion Components  
Y
Device Connection Diagrams and Pin Definitions  
Y
Family Device Differences  
(DP8419 vs DP8409A, 8417, 8418, 8419X)  
Y
Each device is available in plastic DIP, Ceramic DIP, and  
Plastic Chip Carrier (PCC) packaging. (Continued)  
Mode of Operation  
(Descriptions and Timing Diagrams)  
Y
Application Description and Diagrams  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
PALÉ is a registered trademark of and used under license with Monolithic Memories, Inc.  
Y
DC/AC Electrical Specifications, Timing Diagrams and  
Test Conditions  
System Diagram  
TL/F/8396–25  
C
1995 National Semiconductor Corporation  
TL/F/8396  
RRD-B30M105/Printed in U. S. A.  
1234567...28

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